Abstract: A clock generator for producing a pair of nonoverlapping clock signals. Each of a pair of output clock signals is generated by an associated AND gate having a first input connected directly to a clock input and having a second input connected through a delay element. Mechanisms are included to sense the amount of delay introduced by this delay element and to select a new delay value when the sensed delay is outside of an operating range.

Abstract: A clock generator for producing a pair of nonoverlapping clock signals. In one embodiment, a flip-flop functions as a state machine to clock a pair of complementary switches that direct successive pulses of a clock signal alternately to one and then the other of a pair of output clock signal ports. In another embodiment, each of a pair of output clock signals is generated by an AND gate having a first input connected directly to a clock input and having a second input connected through a delay element. Mechanisms are included to sense the amount of delay introduced by this delay element and to select a new delay value when the sensed delay is outside of an operating range.

Abstract: A clock plane is embedded in the housing of a semiconductor chip package where the plane is connected to two or more clock pads on the semiconductor die through vias, bonding fingers and bonding wires. The two or more clock pads are connected by one or more clock lines. The clock plane is connected by means of a via to a clock iput pin. In this manner, a clock signal fed to the clock input pin is driven through the one or more clock line with its tributaries from two separate locations by two or more input clock pads. This reduces clock skew and permits a smaller area of the die surface to be taken up by the clock lines.