Abstract: A system in a processing device having at least one application including application data in a format in an application data store. The system includes: a system data store associated with the processing device including a representation of a previous state of application data in the application data store; a difference engine generating difference information associated with a change to said application data store; and an application interface, interpreting application data for the difference engine. The difference engine may further comprise a delta engine comparing the change to said application data store to said system data store to construct difference information. In a further aspect, a method for updating data files in a first system is provided.

Abstract: A system and method for synchronizing devices which can couple to the Internet, or any network. The system includes a first sync engine on the first system interfacing with data on the first system to provide difference information. A data store is coupled to the network and in communication with the first and second systems. A second sync engine is provided on the second system coupled to receive the difference information from the data store via the network, and interface with data on the second system to update said data on the second system with said difference information. Difference information is transmitted to the data store by the first sync engine and received from the data store from the second sync engine.

Abstract: A method and apparatus for socket-based design with reusable intellectual property (IP) includes a chip integration system (CIS) that provides designers with a convenient method to create and describe a system on a chip (SOC) design independent of design flow. A Chip Integration Description Language (CIDL) is also disclosed that provides a mechanism for defining interfaces between IP cores in a way that isolates a system designer from much of the connection information previously required is also disclosed. Using CIDL, a system designer is able to rapidly connect multiple blocks of intellectual property (IP) based upon the functionality of the blocks rather than traditional hardware-specific connection methods. The details pertaining to specific connections that may be needed are encapsulated within a CIDL-based file that is typically written by the IP core designer. The actual connection of signals between blocks of IP, however, is performed by a CIDL compiler that uses the CIDL file(s) as input.

Abstract: A difference information receiver, a difference information transmitter and a difference information synchronizer which cooperate in a system or device to update data in the device with data received from other systems, or provide data for other systems to use in updating themselves are disclosed. A difference receiver in a device having at least one application data destination having a format includes a difference engine receiving difference information associated with a change to said at least one application data destination; and an application interface, applying said difference information to said at least one data destination. A method for updating data files in a system is also disclosed. The method may include the steps of: receiving difference information for a subset of said data files; and applying said difference information to said subset of said data files.

Abstract: A difference information receiver, a difference information transmitter and a difference information synchronizer which cooperate in a system or device to update data in the device with data received from other systems, or provide data for other systems to use in updating themselves are disclosed. A difference receiver in a device having at least one application data destination having a format includes a difference engine receiving difference information associated with a change to said at least one application data destination; and an application interface, applying said difference information to said at least one data destination. A method for updating data files in a system is also disclosed. The method may include the steps of: receiving difference information for a subset of said data files; and applying said difference information to said subset of said data files.

Abstract: The invention provides a knowledge management system particularly suited for use in the integrated circuit design environment. The system allows administrators to define standardized component types. Instantiated components versions comprise “deliverables” and “attributes.” Deliverables comprise a file or directory of files or groups of files or directories that perform a common function and are characterized by the system in a standardized manner. Attributes comprise metadata describe the component version. By the abstraction of design files into deliverables, the systems can work with design files originating from any source and having different structures and still make those design files available by other designers in a uniform manner for efficient reuse of pre-qualified components. Tasks in the design flow can be tracked in the system. The system may also include a communications application, an issue tracking application, and an audit trail application.

Abstract: A difference information receiver, a difference information transmitter and a difference information synchronizer which cooperate in a system or device to update data in the device with data received from other systems, or provide data for other systems to use in updating themselves are disclosed. A difference receiver in a device having at least one application data destination having a format includes a difference engine receiving difference information associated with a change to said at least one application data destination; and an application interface, applying said difference information to said at least one data destination. A method for updating data files in a system is also disclosed. The method may include the steps of: receiving difference information for a subset of said data files; and applying said difference information to said subset of said data files.

Abstract: In one aspect, an application object for a synchronization system is provided on a network coupled processing device. The application object may comprise a plurality of objects, each object translating third party data to a universal middle format, including a root object providing an entry point into individual application databases; and at least one child object; and at least one interface object.

Abstract: A method and apparatus for generating integrated circuit test patterns (218) to test a functionality of integrated circuits. Module test stimuli (202) for each module present in an integrated circuit (10) are generated and retained (102). The module test stimuli (202) are translated to module drive patterns (206). Module expected patterns (210) are determined based on the module drive patterns (206) or module test stimuli (202) using module models (208). Integrated circuit data (216) describing the structure and timing of the integrated circuit (10) is used to translate the module patterns (212) into integrated circuit test patterns (218). The integrated circuit test patterns (212) are validated (220), transformed to test vectors (226), and the test vectors (226) are applied to the external connections of the integrated circuit (10) to test a functionality of the integrated circuit (10). A data processing system (300) creates the integrated circuit test patterns (218).

Abstract: A single-chip microcontroller (30) includes a central processing unit (CPU) (31) and several memory-mapped peripherals (32, 33, 34, 35) connected to internal address (37) and data (38) buses. The microcontroller (30) includes a test port (40) for receiving test data and providing the test data to the address (37) and data (38) buses to access the memory-mapped peripherals (32, 33, 34, 35) directly. The microcontroller (30) thus allows testing of the memory-mapped peripherals (32, 33, 34, 35) without CPU overhead, significantly reducing test time. The test port (40) includes a shift register (44) which selectively updates address high, address low, and data fields using the test data so that a field need not be re-entered if it doesn't change between test cycles. The test port (40) receives the test data and test control signals via signal lines shared with a general purpose input/output (GPIO) port (33) and requires only one independent control signal line.

Abstract: A microprocessor including unprime registers for use during normal operation, prime registers for use during interrupts, a normal register set for use during normal operation and conventional interrupt operations, an alternate register set for use during fast interrupt operations, and a memory stack. Three status bits are used to indicate that one or more fast interrupts have been initiated but not completed, that a fast interrupt is occurring but there are no other fast interrupts being processed, and that the CPU is currently processing a fast interrupt. These status bits indicate if there is a recursion jeopardy and are used to control the flow of information between the normal and alternate register sets and the memory stack in order to prevent recursion.