Abstract: A bipolar transistor arrangement with compensation for the distortion component (Id) in the collector current (Io+Id) of a transistor (T1), which component is caused by the logarithmic base-emitter voltage thereof. In order to provide this compensation a sub-current (Is) proportional to the emitter current (I+Ie) is generated. This sub-current is fed through an element (7) comprising at least one semiconductor junction. By means of a voltage-to-current converter (8) the logarithmic voltage appearing across this element is converted into a correction current (Ir) proportional to the distortion component (Id) and is applied to the collector of the transistor (T1) in order to compensate for the distortion component (Id) flowing in a load circuit (Rc) connected to the collector. The arrangement is suitable for use in voltage-to-current converters made up of bipolar transistors.

Abstract: An interpolation circuit for an A/D converter comprises a first and a second pair of inputs (2, 2'; 3, 3') and at least three pairs of outputs (20, 20'; 24, 24'; 21, 21'). The pairs of inputs receive pairs of two input signals (V.sub.1, V.sub.1c, V.sub.5, V.sub.5c) which are substantially complementary to one another. At least two pairs of outputs (20, 20'; 24, 24') supply pairs of two substantially complementary output signals. A first output (21) of the third pair of outputs (21, 21') is coupled to a first input (2) of the first pair of inputs (2, 2'). The second output (21') of the third pair of outputs is connected to a circuit node other than one of the inputs of the first pair of inputs. This node may be, for example, the first input (3') of the second pair of inputs (FIG. 9). Another possibility is to make the node one end (38) of an impedance element (32) which has its other end coupled to the second input (2') of the first pair of inputs (FIG. 3).

Abstract: An integrated semiconductor circuit, in which the D.C. part of the wiring containing only D.C. information lies on a part of the insulating layer located on the surface which is considerably thinner than the parts of the insulating layer under wiring parts not forming part of the D.C. wiring. Preferably, for this purpose a substrate contact diffusion connected to a reference potential is provided under the D.C. wiring parts. As a result, H.F. interference signals on the D.C. wiring are reduced so that noise and distortion are considerably reduced.

Abstract: An interpolation circuit for use in an A/D converter comprises a first and a second pair of inputs (2, 2'; 3, 3') and at least three pairs of outputs (20, 20'; 24, 24'; 21, 21'). The pairs of inputs receive pairs of two input signals (V.sub.1, V.sub.1c, V.sub.5, V.sub.5c) which are substantially complementary to one another. At least two pairs of outputs (20, 20'; 24, 24') supply pairs of two substantially complementary output signals. A first output (21) of the third pair of outputs (21, 21') is coupled to a first input (2) of the first pair of inputs (2, 2'). The second output (21') of the third pair of outputs is connected to a circuit node which is not one of the inputs of the first pair of inputs. This node may be, for example, the first input (3') of the second pair of inputs (FIG. 9). Another possibility is to make the node one end (38) of an impedance element (32) whose other end is coupled to the second input (2') of the first pair of inputs (FIG. 3).

Abstract: An integrated resistor is constituted by a doped resistance body in a semiconductor substrate which is coated with a layer of insulating material having local apertures in which metal end contacts (2a, 3a) and tapping contacts (4a, 5a, 6a) are provided. The width of each tapping contact (4a, 5a, 6a) is smaller than the width of the doped zone and, viewed in the longitudinal direction of the resistance body, the tapping contacts (4a, 5a, 6a) do not overlap.

Abstract: In conventional digital-to-analog converters one of a number of multi-emitter transistors is driven by means of the select logics, the emitters of which are connected selectively to a group of data lines. The output circuits connected to the data lines further receive a reference voltage to be able to detect the condition on the data lines. In the analog converter according to the invention each data line is constructed so as to be complementary in which the emitters which in the prior art circuit arrangement are connected to the first group of data lines are coupled in the same manner to a first group of data lines while the remaining emitters are now connected to complementary lines from the second group. The output circuits which are connected to the data lines receive a logic signal of a data line and the complementary logic signal of the associated complementary data line. The result is that the voltage step which is presented to the inputs of the output circuits is twice as large.

Abstract: In an analog-to-digital converter circuit comprising a comparison circuit per tap of a potential divider. The comparison circuits are arranged in groups each controlling a respective differential amplifier. In a group only one output of each comparison circuit is connected to an output of the subsequent comparison circuit operating in the opposite sense and the odd outputs of the group of outputs thus obtained are connected via a first group of emitter followers to a first input of one of the differential amplifiers, while the even outputs are connected via a second group of emitter followers to a second input of this differential amplifier.

Abstract: In order to avoid errors due to time differences between output signals containing coarse bit information and fine bit information, an insertion circuit (77) is used in an analog-to-digital converter, having a coarse converter (5, 33) and two folding circuits (9, 13) which are each followed by a fine converter (19, 25, 33), to replace changing coarse bit information with changing fine bit information in the output signals.

Abstract: For the automatic calibration of an analog-to-digital converter an analog calibration quantity is measured and the digital signal is compared with a digital calibration signal associated with the calibration quantity. A digital difference signal is applied to a register for influencing its counting capacity, while the register contents of pulses counted during the measurement also represents one of the parameters involved in the analog-to-digital conversion. Because of the fully digital character of the calibration, this calibration can be performed very rapidly and accurately.

Abstract: The invention provides a substantial improvement of a known rectifying circuit for a.c. signals by adding a circuit which measures the d.c. unbalance at the output and subsequently cancels said unbalance by feeding back compensation currents to the rectifying circuit. A dynamic range of 1 to 10,000 or more is then attainable. The rectifying circuit supplies a current whose shape is similar to that of the a.c. input signal, thus enabling r.m.s. values to be measured, for example in voltmeters.