Abstract: One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.

Abstract: Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.

Abstract: Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.

Abstract: Method for forming a semiconductor device having an capacitor, where the capacitor is in-laid in a cavity formed in the semiconductor substrate and part of a high density memory. One embodiment first forms a bottom electrode in the cavity and then fills the cavity with a sacrificial layer to allow chemical mechanical polishing (CMP) of at least one of the capacitor electrodes. After removing portions of the bottom electrode and portions of the sacrificial layer, a dielectric layer is formed. A top electrode is then formed over the dielectric layer. The dielectric layer so formed isolates the bottom electrode from the top electrode preventing shorting and leakage currents. In one embodiment, a single top electrode layer is formed for multiple bottom electrodes, reducing the complexity of the memory circuit.

Abstract: A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

Abstract: An inductive-write magnetoresistive-read horizontal head for magnetic recording having two polarization conductors. The two polarization conductors are used to simultaneously activate a MR sensor and to disable the write head during the read back process to eliminate the secondary read back signal from the inductive-write head. During the read process, the current through a first conductor biases the MR stripe while current through the second conductor generates an applied field to switch the magnetization of the Permalloy (NiFe) in the write head pole and reduce the permeability. The head incorporates write-wide read-narrow head attributes and has the reliability advantages associated with yoke or recessed MR or GMR structures. The magnetoresistive stripe may be disposed directly in the gap of the heads or it may be recessed.

Abstract: An inductive-write magnetoresistive-read horizontal head for magnetic recording having two polarization conductors. The two polarization conductors are used to simultaneously activate a MR sensor and to disable the write head during the read back process to eliminate the secondary read back signal from the inductive-write head. During the read process, the current through a first conductor biases the MR stripe while current through the second conductor generates an applied field to switch the magnetization of the permalloy in the write head pole and reduce the permeability. The head incorporates write-wide read-narrow head attributes and has the reliability advantages associated with yoke or recessed MR or GMR structures. The magnetoresistive stripe may be disposed directly in the gap of the heads or it may be recessed.

Abstract: A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

Abstract: A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.

Abstract: An NVRAM array (30) has a portion (31) associated with a drive line segment (DSL.sub.11). The drive line segment (DSL.sub.11) is coupled to a drive line (DL1) by a control transistor (32). The layout allows a conductive member (112) that is part of lo the drive line segment (DSL.sub.11) to be formed at about the same elevation as the memory capacitors (118). The layout further allows interconnects (136) for the drive lines (DL1, DL.sub.2) and bit lines (BL.sub.11, BL.sub.12, BL.sub.13, BL.sub.14) to be formed over the control and memory transistors (32, 34), as opposed to between the transistors. The process forms a small and reliable NVRAM device.

Abstract: A combination suspension and transducer magnetic head for longitudinal recording which can be used for contact recording and flying above the media. The transducer includes a horizontal first pole piece and a horizontal and vertical sectioned second pole piece. The magnetic gap is formed between the first pole piece and the vertical section of the second pole piece. The suspension layers are formed mainly from the insulation layer that separate the first horizontal pole piece and the horizontal section of the second pole piece, and an insulation layer that covers and protects the transducer layers. The layers of the combination head are deposited on a wafer in a row and column configuration. A release layer is deposited on the substrate first and then the individual thin film layers of the transducer are deposited. A horizontal first pole piece is formed. A horizontal section of a second pole piece is formed and activated by a conductor coil wound around the horizontal section.

Abstract: A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.

Abstract: A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).

Abstract: A new and improved unshielded horizontal magnetoresistive head is disclosed which utilizes multiple pairs of magnetoresistive elements. The present invention provides a device which is characterized by reduced output signal undershoot amplitudes, and an increased central peak pulse amplitude, while not significantly affecting the resolution of the device. The device is also characterized by increased signal to noise and signal to interference ratios. Magnetoresistive elements utilized in the device may be fabricated and/or manufactured by simplified processes, resulting in fabrication, manufacturing and cost benefits for the magnetoresistive head. Any number of additional magnetoresistive element pairs may be utilized dependent on the accuracy and resolution required by the specific application.

Abstract: A nonvolatile random access memory (60) includes a ferroelectric memory array (62). The memory array (62) includes memory cells (86-89 and 91-96) arranged in intersecting rows and columns, where the memory cells (86-89 and 91-96) are coupled to bit lines and word lines. Drive lines are disposed parallel to the bit lines and drive line segments are disposed parallel to the word lines. A drive line segment is coupled to a predetermined number of the memory cells of a row. Coupling transistors (80, 82, 84, and 90) couple a drive line segment to a drive line in response to the word line being selected. The ferroelectric memory array (60) provides the advantage of eliminating a change in the polarization state of non-accessed memory cells connected to a selected drive line, and also provides the advantage of reduced energy consumption.

Abstract: A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).

Abstract: Continuous fiber reinforced oriented mesogen-containing resin matrix composites are prepared by (A) saturating a continuous fiber substrate material with a curable composition comprising (1) at least one mesogen-containing resin which contains an average of more than one vicinal epoxide group, thiirane group, cyanate group or vinyl ester group per molecule; and, optionally, (2) a curing amount of at least one curing agent and/or curing catalyst therefor; (B) arranging one or more saturated continuous fiber substrate material(s) formed in step (A) into a desired configuration; (C) subjecting the arranged saturated continuous fiber substrate material(s) from step (B) to a temperature which causes the mesogen-containing resin to convert to a liquid crystalline state; (D) subjecting the heated arranged saturated continuous fiber substrate material(s) from step (C) to a pressure sufficient to cause flow induced shear in the interstices of said continuous fiber substrate; (E) subjecting the continuous fiber substra

Abstract: A local interconnect structure is formed in a semiconductor device. In one form, the semiconductor device has two conductive features (one of 54) and (56) which are to be electrically connected. A layer of metal (62), for instance titanium, is deposited on the device. The layer of metal is patterned to form a strap (64) which connects the two conductive features. After patterning the layer of metal to form the strap, the strap is thermally nitrided to form a conductive metal nitride local interconnect (66).

Abstract: An unshielded horizontal magnetoresistive head for magnetic sensing and reading devices. The horizontal unshielded magnetoresistive head is comprised of two magnetoresistive elements separated by a gap and a conductive cross member which electrically connects the magnetoresistive elements together and to a common electrical point such as system ground. A differential voltage sensing circuit is connected across the magnetoresistive elements for sensing voltage variations when magnetic data is sensed by the head. The present invention further facilitates a more simplified fabrication process which results in cost savings and more efficient fabrication methods and procedures.

Abstract: An integrated circuit includes a patterned aluminum based interconnect clad on the top and side portions with a layer of transition metal. The cladding of transition metal prevents the formation of both vertical hillocks and lateral protrusions. Preventing these formations increases the reliability of an interconnect by significantly reducing passivation cracking and electrical shorting between interconnects which result from vertical hillock and lateral protrusion formations.