Abstract: A computer which has multiple central processing units where at least one of the processors is a spare and unused for normal system operation, provides a mechanism for transferring the micro-architected state of a checkstopped processor to a spare processor. Each processor has a set of registers in the central processing unit where the micro-architected state of the processor is kept and these registers are accessible by millicode or microcode running on that processor. A checkstop of a processor is detected by the system, the micro-architected state of that processor is extracted and returned to the system where that state can be loaded into a spare processor in the system and processing resumed without interruption.

Abstract: A computer which has multiple central processing units where at least one of the processors is a spare and unused for normal system operation, provides a mechanism for transferring the micro-architected state of a checkstopped processor to a spare processor. Each processor has a set of registers in the central processing unit where the micro-architected state of the processor is kept and these registers are accessible by millicode or microcode running on that processor. A checkstop of a processor is detected by the system, the micro-architected state of that processor is extracted and returned to the system where that state can be loaded into a spare processor in the system and processing resumed without interruption.

Abstract: A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegiance or association of systems to particular storage spaces is established when each system is initialized and enables a simple interface between user program(s) and message passing hardware consisting primarily of instructions for moving control and data blocks between the program addressable space and the hardware addressable space.

Abstract: A data processing system operating under a multiprocessing hypervisor program subject to I/O interrupts during a polling interval of the hypervisor program includes one or more processors for executing the hypervisor program and host system and one or more guest systems under the hypervisor program, a storage system connected to the processor's by a bus for storing instructions, data and control information associated with the systems being executed by the processor, the storage system may be partitioned into a number of separate areas each associated with one of the concurrently operating systems, an input/output subsystem for generating I/O interrupts to the processors, apparatus for testing to determine if the system is operating in an interpretive execution mode, apparatus for determining whether a dedicated region facility is active, apparatus for testing whether an I/O enablement mask for a guest system has been set, apparatus for setting a flag if the guest system I/O enablement mask is set, apparatus

Abstract: A data processing system operated with multiple levels of virtual machine guests under a host control program. The second level of guests are invoked, operated, and terminated without host intervention, as has been required in prior systems, to significantly increase the operating efficiency of the system. Address translation is done by providing machine capability to translate second level guest addresses to real memory addresses taking advantage of the first level guest being located at a simple offset within real memory. Special facilities for second level guests periodically test for timing interruptions for second level guests and update the second level guest timing facilities.

Abstract: A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB.

Abstract: An apparatus and method are established for recognizing guest virtual machines which require only a subset of interpretive execution facilities. The interpretive execution initialization process recognizes subset candidates and bypasses initialization of those facilities not required by the candidates. The candidates are typically short duration jobs and a reduction of initialization and termination overhead creates a substantial performance improvement. The translation lookaside buffer operation is modified to flag subset guest entries as host entries and to associate a unique segment table origin with each subset guest. This allows the TLB entries to remain between guest machine dispatches eliminating TLB purge time and allowing potential reuse of TLB entries if the same guest is repeatedly dispatched within a short time period. The guest machine state description is modified to flag subset candidates based on address translation and timing requirements.

Abstract: A method of controlling processing in a computer, particularly real-time processing, is performed using computer data objects. Real-time or other input data received from data sources is classified according to pre-stored control data. The control data defines which data source provides the real-time data, how the real-time data is to be processed, where the real-time data is to be stored and what reports the real-time data will be used in. The classified real-time data becomes a computer data object with its associated control data and all subsequent processing is performed on the computer data object.