Abstract: Method for detecting when first and second signal patterns have occurred on a split-transaction bus having transaction identifying indicia: Signal patterns occurring on the bus are compared with a first stored signal pattern. If a match is detected, the transaction identifying indicia that were associated on the bus with the first signal pattern are stored, and a first detection signal is asserted and held asserted. Signal patterns on the bus are then compared with a second stored signal pattern, and transaction identifying indicia occurring on the bus are compared with the indicia previously stored. A match signal is asserted when the first detection signal is asserted and, simultaneously, matches are detected for both of the second signal pattern comparison and the transaction identifying indicia comparison. Circuitry for implementing the method: First comparison circuitry asserts a first detection signal when a first signal pattern is detected on the bus.

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements.

Abstract: A computer system has a multi-tiered bus system. The multi-tiered bus system includes one or more local buses and a central bus connected to each local bus by a bus interface. In order to maintain one global view of transaction ordering, the processors on each local bus record bus transactions in an order on which the bus transactions appear on the central bus. To do this, bus transactions which are initiated on any local bus are forwarded to the central bus by the corresponding bus interface. The processors connected to the local bus do not record bus transactions when they are initiated on the local bus. Every transaction which occurs on the central bus is echoed back to every local bus by the corresponding bus interface. Each processor records bus transactions at the time they are echoed back to the local bus.

Abstract: A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle.