Abstract: A disclosed circuit arrangement includes an interconnect circuit, a processor, a first memory circuit, a proxy memory circuit, and a decryption circuit. The interconnect circuit receives a first transaction from one of the one or more processors and transmits the first transaction to the proxy memory circuit in response to a first address in a first transaction. The proxy memory circuit translates the first address into a second address of the first memory circuit, generates a second transaction including the second address, transmits the second transaction to the interconnect circuit, and receives encrypted data from the first memory circuit in a response to the second transaction. The decryption circuit decrypts the encrypted data into decrypted data, and the proxy memory circuit transmits the decrypted data to the one processor in a response to the first transaction.

Abstract: An approach for management of memory in a programmable integrated circuit (IC) includes configuring a memory map of the programmable IC with an association of a first subset of addresses of memory address space of the programmable IC and physical memory of the programmable IC. The memory map is further configured with an association of a second subset of addresses of the memory address space and a virtual memory block. At least a portion of a cache memory of the programmable IC is locked to the second subset of addresses.