Abstract: A method for digitizing at least a portion of a selected analog input signal of a plurality of analog input signals by using a multiplexer having a plurality of channels is provided. Each channel for the multiplexer is associated with at least one of the analog input signals and is associated with a pair of select signals, and wherein each channel includes a cell having an input terminal, an output terminal, and a boosted NMOS switch. According to the method, a first select signal from each pair of select signals is asserted to decouple the input and output terminals for each cell. A boost capacitor is also charged during the non-sampling or conversion phase while the first select signal from each pair of select signals is asserted.

Abstract: A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a first terminal of a corresponding capacitor (22) and a second terminal coupled to receive an analog input signal (VSIG). A third terminal of the sampling switch circuit is coupled to an intermediate conductor (19). Each switching circuit (33) also includes a low-voltage conversion switch circuit (30) coupled to the intermediate conductor (19) and a combinational logic circuit (12) applying low-voltage signals to the conversion switch circuit and a level-shifting circuit (16) that generates corresponding high-voltage signals (HV_SIG_DRV) which control coupling of the first terminal (28) to the analog input signal and the intermediate conductor.

Abstract: A method for digitizing at least a portion of a selected analog input signal of a plurality of analog input signals by using a multiplexer having a plurality of channels is provided. Each channel for the multiplexer is associated with at least one of the analog input signals and is associated with a pair of select signals, and wherein each channel includes a cell having an input terminal, an output terminal, and a boosted NMOS switch. According to the method, a first select signal from each pair of select signals is asserted to decouple the input and output terminals for each cell. A boost capacitor is also charged during the non-sampling or conversion phase while the first select signal from each pair of select signals is asserted.

Abstract: A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a first terminal of a corresponding capacitor (22) and a second terminal coupled to receive an analog input signal (VSIG). A third terminal of the sampling switch circuit is coupled to an intermediate conductor (19). Each switching circuit (33) also includes a low-voltage conversion switch circuit (30) coupled to the intermediate conductor (19) and a combinational logic circuit (12) applying low-voltage signals to the conversion switch circuit and a level-shifting circuit (16) that generates corresponding high-voltage signals (HV_SIG_DRV) which control coupling of the first terminal (28) to the analog input signal and the intermediate conductor.

Abstract: A method and circuit for gain and/or offset correction in a CDAC circuit are provided. The gain and/or offset correction can be realized by adjusting the sampling capacitance of a capacitor array, with a positive array of the CDAC circuit being trimmed for gain correction, and a negative array of the CDAC circuit being trimmed for offset correction. Accordingly, corrections to variations in gain and/or offset caused by process variations can be suitably addressed. To facilitate gain correction, an exemplary CDAC circuit comprising an N-bit capacitor array includes on the positive side of the capacitor array an additional capacitor configured to capture the sampling voltage. An exemplary CDAC circuit can also be configured to have one or more capacitors shifted out of the total capacitance of the capacitor array, and thus reduce the amount of charge stored during sampling.

Abstract: A CDAC circuit is provided that can operate at low supply voltages, for example, at supply voltages of 2.5 volts or less. To accomplish low voltage operation, switches in the CDAC circuit, such as sampling bit switches, mid-point switches or auto-zero switches, are gate-boosted to permit the voltage at the transmission gates to exceed the threshold voltage and thus permit the transmission gates to effectively operate. As a result, the CDAC can continue to operate, even with the existence of lower power supply voltages. In accordance with an exemplary embodiment, a gate-boosting circuit comprises a pair of N-channel transistor devices and a charging capacitor configured to provide a gate-boosting voltage to the transmission gates. In addition, the gate boosting circuit can comprise conventional CMOS devices, rather than more expensive low threshold MOSFET devices.

Abstract: A CDAC circuit is provided that can operate at low supply voltages, for example, at supply voltages of 2.5 volts or less. To accomplish low voltage operation, switches in the CDAC circuit, such as sampling bit switches, mid-point switches or auto-zero switches, are gate-boosted to permit the voltage at the transmission gates to exceed the threshold voltage and thus permit the transmission gates to effectively operate. As a result, the CDAC can continue to operate, even with the existence of lower power supply voltages. In accordance with an exemplary embodiment, a gate-boosting circuit comprises a pair of N-channel transistor devices and a charging capacitor configured to provide a gate-boosting voltage to the transmission gates. In addition, the gate boosting circuit can comprise conventional CMOS devices, rather than more expensive low threshold MOSFET devices.