Abstract: In a silicon integrated circuit manufacturing process a layer of polysilicon is ion implanted with an n-type dopant and etched through a mask with a fluorine:chlorine mixture. The etchant undercuts at the mask to an extent dependent on the ratio of chlorine:fluorine and on the dopant level. By appropriately selecting that ratio and dopant level, polysilicon islands having a rounded profile can be achieved, this being most efficacious for subsequent deposition onto the polysilicon.

Abstract: In a double polysilicon integrated circuit processing method a first level polysilicon is used for FET gate fabrication, a second level is used for interconnection and both levels are used in the fabrication of analog capacitors over field oxide regions. By the invention, capacitors are also fabricated in the FET device well by implanting dopant through the second level polysilicon at the same time that dopant is implanted directly into other regions of the substrate to a greater depth and dopant level concentration so as to function as an FET source. The method is particularly adapted to fabricating DRAM memories.