Patents by Inventor Robert E. Walkup

Robert E. Walkup has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Opcode counting for performance measurement
    Patent number: 10713043
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • OPCODE COUNTING FOR PERFORMANCE MEASUREMENT
    Publication number: 20180203693
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Opcode counting for performance measurement
    Patent number: 9921831
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • OPCODE COUNTING FOR PERFORMANCE MEASUREMENT
    Publication number: 20170068536
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Application
    Filed: October 12, 2016
    Publication date: March 9, 2017
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • Opcode counting for performance measurement
    Patent number: 9473569
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • OPCODE COUNTING FOR PERFORMANCE MEASUREMENT
    Publication number: 20150347141
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Application
    Filed: July 15, 2015
    Publication date: December 3, 2015
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • Opcode counting for performance measurement
    Patent number: 9106656
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • OPCODE COUNTING FOR PERFORMANCE MEASUREMENT
    Publication number: 20140052970
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • Opcode counting for performance measurement
    Patent number: 8571834
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • Optimizing layout of an application on a massively parallel supercomputer
    Patent number: 8117288
    Abstract: A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=?i,jC(i,j)H(i,j)? where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gyan V. Bhanot, Alan Gara, Philip Heidelberger, Eoin M. Lawless, James C. Sexton, Robert E. Walkup
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • OPCODE COUNTING FOR PERFORMANCE MEASUREMENT
    Publication number: 20110172969
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • Functional sugar polymers from inexpensive sugar sources and apparatus for preparing same
    Publication number: 20030044942
    Abstract: A process for preparing functional sugar polymers comprising transferring a monosaccharide or oligosaccharide to an acceptor, removing by-products, separating polymers which have not achieved the desired chain length and recycling these underdeveloped polymers, and an apparatus for producing same.
    Type: Application
    Filed: April 23, 2002
    Publication date: March 6, 2003
    Inventors: Steven J. Catani, Kathleen S. Laurenzo, Juan L. Navia, Robert E. Walkup
  • Functional sugar polymers from inexpensive sugar sources and apparatus for preparing same
    Patent number: 6423833
    Abstract: A process for preparing functional sugar polymers comprising transferring a monosaccharide or oligosaccharide to an acceptor, removing by-products, separating polymers which have not achieved the desired chain length and recycling these underdeveloped polymers, and an apparatus for producing same.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: July 23, 2002
    Inventors: Steven J. Catani, Kathleen S. Laurenzo, Juan L. Navia, Robert E. Walkup
  • Recovery of sucralose intermediates
    Patent number: 5530106
    Abstract: There is disclosed a process for recovering sucralose-6-ester from a feed mixture of 6-O-acyl-4,1',6'-trichloro-4,1',6'-trideoxygalactosucrose in a reaction medium comprising a tertiary amide (such as N,N-dimethylformamide), wherein said process comprises removing a major proportion of said tertiary amide by steam distillation. In preferred aspects of the invention, the steam distillation is followed by extraction and then purification by crystallization or crystal aging to recover sucralose-6-ester in good yield.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: June 25, 1996
    Assignee: McNeil-PPC, Inc.
    Inventors: Juan L. Navia, Robert E. Walkup, David S. Neiditch
  • Production of sucralose without intermediate isolation of crystalline sucralose-6-ester
    Patent number: 5498709
    Abstract: There is disclosed a process for producing sucralose from sucralose-6-ester whereby the sucralose-6-ester is deacylated directly either prior to or after removal of the tertiary amide reaction vehicle from the neutralized chlorination reaction mixture, to produce an aqueous solution of sucralose plus salts and impurities, from which sucralose is recovered by extraction and is then preferably purified by crystallization.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: March 12, 1996
    Assignee: McNeil-PPC, Inc.
    Inventors: Juan L. Navia, Robert E. Walkup, Nicholas M. Vernon, David S. Neiditch
  • Sucralose pentaester production
    Patent number: 5298611
    Abstract: A process for producing substantially pure sucralose pentaester from a mixture of 6-O-acyl-4,1' ,6' -trichloro-4,1',6'-trideoxygalactosucrose in a reaction medium comprising a tertiary amide, wherein said process comprises the steps of:(a) recovering the 6-O-acyl-4,1' ,6' -trichloro-4,1' ,6' -trideoxygalactosucrose from said mixture;(b) peracylating the 6-O-acyl-4,1' ,6' -trichloro-4,1' ,6' -trideoxygalactosucrose product of step (a) to produce thereby 4,1',6' -trichloro-4,1' ,6' -trideoxygalactosucrose pentaester; and(c) crystallizing the 4,1',6' -trichloro-4,1' ,6' -trideoxygalactosucrose pentaester product of step (b) to produce substantially pure 4,1',6' -trichloro-4,1' ,6' -trideoxygalactosucrose pentaester.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: March 29, 1994
    Assignee: McNeil-PPC, Inc.
    Inventors: Juan L. Navia, Robert E. Walkup, Nicholas M. Vernon, Robert E. Wingard, Jr.