Patents by Inventor Robert E. Wallis

Robert E. Wallis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9844169
    Abstract: A multi-chip module is provided including a multiplier configured to multiply a frequency of an input signal into a predetermined Ka-band frequency center channel, a modulator configured to modulate the center channel, and an amplifier configured to amplify a modulated signal for output.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: December 12, 2017
    Assignee: The Johns Hopkins University
    Inventors: Daniel E. Matlin, Sheng Cheng, Seppo J. Lehtonen, John E. Penn, Perry M. Malouf, Matthew P. Angert, Christopher B. Haskins, Avinash Sharma, Jacob P. Treadway, Robert E. Wallis
  • Publication number: 20160126891
    Abstract: A multi-chip module is provided including a multiplier configured to multiply a frequency of an input signal into a predetermined Ka-band frequency center channel, a modulator configured to modulate the center channel, and an amplifier configured to amplify a modulated signal for output.
    Type: Application
    Filed: September 1, 2015
    Publication date: May 5, 2016
    Inventors: Daniel E. Matlin, Sheng Cheng, Seppo J. Lehtonen, John E. Penn, Perry M. Malouf, Matthew P. Angert, Christopher B. Haskins, Avinash Sharma, Jacob P. Treadway, Robert E. Wallis
  • Patent number: 9256559
    Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Hart, Liang Jiang, Anil Kalavakolanu, Shannon D. Moore, Robert E. Wallis, Evelyn T. Yeung
  • Patent number: 9032122
    Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Hart, Liang Jiang, Anil Kalavakolanu, Shannon D. Moore, Robert E. Wallis, Evelyn T. Yeung
  • Publication number: 20150052279
    Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Brian W. Hart, Liang Jiang, Anil Kalavakolanu, Shannon D. Moore, Robert E. Wallis, Evelyn T. Yeung
  • Publication number: 20150052281
    Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.
    Type: Application
    Filed: December 10, 2013
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Brian W. Hart, Liang Jiang, Anil Kalavakolanu, Shannon D. Moore, Robert E. Wallis, Evelyn T. Yeung
  • Patent number: 6909324
    Abstract: A high-efficiency solid state power amplifier (SSPA) for specific use in a spacecraft is provided. The SSPA has a mass of less than 850 g and includes two different X-band power amplifier sections, i.e., a lumped power amplifier with a single 11-W output and a distributed power amplifier with eight 2.75-W outputs. These two amplifier sections provide output power that is scalable from 11 to 15 watts without major design changes. Five different hybrid microcircuits, including high-efficiency Heterostructure Field Effect Transistor (HFET) amplifiers and Monolithic Microwave Integrated Circuit (MMIC) phase shifters have been developed for use within the SSPA. A highly efficient packaging approach enables the integration of a large number of hybrid circuits into the SSPA.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: June 21, 2005
    Assignee: The Johns Hopkins University
    Inventors: Robert E. Wallis, Sheng Cheng
  • Publication number: 20040027203
    Abstract: A high-efficiency solid state power amplifier (SSPA) for specific use in a spacecraft is provided. The SSPA has a mass of less than 850 g and includes two different X-band power amplifier sections, i.e., a lumped power amplifier with a single 11-W output and a distributed power amplifier with eight 2.75-W outputs. These two amplifier sections provide output power that is scalable from 11 to 15 watts without major design changes. Five different hybrid microcircuits, including high-efficiency Heterostructure Field Effect Transistor (HFET) amplifiers and Monolithic Microwave Integrated Circuit (MMIC) phase shifters have been developed for use within the SSPA. A highly efficient packaging approach enables the integration of a large number of hybrid circuits into the SSPA.
    Type: Application
    Filed: June 2, 2003
    Publication date: February 12, 2004
    Inventors: Robert E. Wallis, Sheng Cheng