Patents by Inventor Robert E. Yui

Robert E. Yui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020072227
    Abstract: A barrier/liner structure (10) and method. First, a refractory metal/metal nitride layer (12) is formed over a structure (18), for example, by metal-organic CVD (MOCVD). Then, the refractory metal/metal nitride layer (12) is exposed to an organosilane, such as diethylsilane, to obtain a silicon-rich surface layer (14).
    Type: Application
    Filed: August 23, 2001
    Publication date: June 13, 2002
    Inventors: Noel Russell, Richard A. Faust, Robert E. Yui, Jiong-Ping Lu
  • Patent number: 5695378
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by a dielectric insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays (12) of microtips (14) are located in mesh spacings (16), within apertures (26) formed in clusters (23) in extraction electrode (22). Microtips (14) are deposited through the apertures (26). The insulating spacer (125) is etched to undercut electrode (22) to connect apertures, forming a common cavity (141) for microtips (14) within each mesh spacing (16). Support beam structures (143) are deposited onto extraction electrode (22), either separately or simultaneously with formation of the microtips (14). The support beam structures (143) span the cavity (141) to support the extraction electrode (22) above the cathode electrode over cavity (141). The etch-out reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: December 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Phil E. Hecker, Jr., Robert E. Yui, Jules David Levine
  • Patent number: 5686782
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by a dielectric insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays (12) of microtips (14) are located in mesh spacings (16), within apertures (26) formed in clusters (23) in extraction electrode (22). Microtips (14) are deposited through the apertures (26). The insulating spacer (125) is etched to undercut electrode (22) to connect apertures, forming a common cavity (141) for microtips (14) within each mesh spacing (16). Support beam structures (143) are deposited onto extraction electrode (22), either separately or simultaneously with formation of the microtips (14). The support beam structures (143) span the cavity (143) to support the extraction electrode (22) above the cathode electrode over cavity (143). The etch-out reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: November 11, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Phil E. Hecker, Jr., Robert E. Yui, Jules David Levine