Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: determining a pacing requirement for host requests based on one or more thresholds; setting a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement; and implementing a memory request flow for a host request based on the pacing requirement and the pacing delay level.

Abstract: Embodiments include methods, systems and computer program products for managing a flash memory device. Aspects include monitoring a percentage of memory of the flash memory device that is in a ready to use state. Aspects also include operating the flash memory device in a first operating mode based on a determination that the percentage is greater than a first threshold value. Aspects further include operating the flash memory device in a second operating mode based on a determination that the percentage has fallen below the first threshold value. Aspects include operating the flash memory device in a third operating mode until the percentage exceeds the first threshold value based on a determination that the percentage has fallen below a second threshold value, which is lower than the first threshold value. The erasing of ready to erase memory block stripes is only performed during the third operating mode.

Abstract: A product, system, and/or method of managing memory media that includes: determining whether the memory system is low on one or more ready-to-use (RTU) Block Stripes needed to form a RTU Block Stripe Set, wherein the memory media has a plurality of Planes in each Die, all the memory media Blocks in each Block Stripe are from the same Die # and the same Plane #, each Block Stripe Set is formed of a plurality of Block Stripes all from the same Die #, and all the Blocks in each RTU Block Stripe Set have been subject to the removal process and the erasure process. The product, system, and/or method includes: establishing a pending request for a removal process and/or an erasure process for one or more determined Die #/Plane # combinations; and prioritizing in the one or more determined Die #/Plane # combinations one or more memory media Blocks for the removal and/or erasure process.

Abstract: A product, system, and/or method of managing memory media that includes: determining whether the memory system is low on one or more ready-to-use (RTU) Block Stripes needed to form a RTU Block Stripe Set, wherein the memory media has a plurality of Planes in each Die, all the memory media Blocks in each Block Stripe are from the same Die #and the same Plane #, each Block Stripe Set is formed of a plurality of Block Stripes all from the same Die #, and all the Blocks in each RTU Block Stripe Set have been subject to the removal process and the erasure process. The product, system, and/or method includes: establishing a pending request for a removal process and/or an erasure process for one or more determined Die #/Plane #combinations; and prioritizing in the one or more determined Die #/Plane #combinations one or more memory media Blocks for the removal and/or erasure process.

Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Abstract: A product, system, and/or method of managing memory media that includes: determining whether the memory system is low on one or more ready-to-use (RTU) Block Stripes needed to form a RTU Block Stripe Set, wherein the memory media has a plurality of Planes in each Die, all the memory media Blocks in each Block Stripe are from the same Die # and the same Plane #, each Block Stripe Set is formed of a plurality of Block Stripes all from the same Die #, and all the Blocks in each RTU Block Stripe Set have been subject to the removal process and the erasure process. The product, system, and/or method includes: establishing a pending request for a removal process and/or an erasure process for one or more determined Die #/Plane # combinations; and prioritizing in the one or more determined Die #/Plane # combinations one or more memory media Blocks for the removal and/or erasure process.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: determining a pacing requirement for host requests based on one or more thresholds; setting a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement; and implementing a memory request flow for a host request based on the pacing requirement and the pacing delay level.

Abstract: Embodiments include methods, systems and computer program products for managing a flash memory device. Aspects include monitoring a percentage of memory of the flash memory device that is in a ready to use state. Aspects also include operating the flash memory device in a first operating mode based on a determination that the percentage is greater than a first threshold value. Aspects further include operating the flash memory device in a second operating mode based on a determination that the percentage has fallen below the first threshold value. Aspects include operating the flash memory device in a third operating mode until the percentage exceeds the first threshold value based on a determination that the percentage has fallen below a second threshold value, which is lower than the first threshold value. The erasing of ready to erase memory block stripes is only performed during the third operating mode.

Abstract: A method and system of managing memory, the method including receiving a request for storage space in the memory system; obtaining a timestamp for a new Logical Unit Number (LUN); allocating a range of logical blocks to the new LUN in accordance with its requested size, the range of logical blocks including a starting logical block and a number of blocks; assigning the timestamp to the new LUN as the LUN creation timestamp; and saving the LUN creation timestamp with other metadata identifying the new LUN and the allocated logical blocks. Methods and system for deleting LUNs and using a deletion timestamp are disclosed as is a process to format a LUN.

Abstract: In an approach to NV SCM data flow with mismatched block sizes, responsive to receiving a command from a host on a memory controller for a storage class memory, whether the command is a write command is determined. Responsive to determining that the command is the write command, the command is inserted into a first buffer. Responsive to the command exiting the first buffer, whether the command generates a cache hit from the internal cache is determined. Responsive to determining that the command generates the cache hit, the write data is written into the internal cache. Responsive to determining that the command does not generate the cache hit, whether an oldest page in the internal cache is dirty is determined. Responsive to determining that the oldest page in the internal cache is dirty, a modified oldest page is written to the internal cache and a second buffer.

Abstract: In an approach to failed media channel recovery throttling, responsive to detecting a programming error on an addressable unit during programming of a block stripe, the block stripe is placed on a recovery/data migration queue. An error counter for the addressable unit on which the programming error occurred is incremented. The block stripes from the recovery/data migration queue are built excluding a specific channel containing the addressable unit on which the programming error occurred. Responsive to determining that the queue for the recovery/data migration is empty, building the block stripes resumes using the plurality of channels, where the specific channel containing the addressable unit on which the programming error occurred is included. Responsive to determining that a number of errors on a specific addressable unit exceeds a predetermined threshold based on the error counter for the specific addressable unit, the specific addressable unit is decommissioned.

Abstract: A method and system of managing memory, the method including receiving a request for storage space in the memory system; obtaining a timestamp for a new Logical Unit Number (LUN); allocating a range of logical blocks to the new LUN in accordance with its requested size, the range of logical blocks including a starting logical block and a number of blocks; assigning the timestamp to the new LUN as the LUN creation timestamp; and saving the LUN creation timestamp with other metadata identifying the new LUN and the allocated logical blocks. Methods and system for deleting LUNs and using a deletion timestamp are disclosed as is a process to format a LUN.

Abstract: A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.

Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Abstract: A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.

Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Abstract: A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.

Abstract: A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.

Abstract: A method and apparatus are provided for dynamically determining a primary adapter in a heterogeneous N-way adapter configuration. Each of the adapters generates information about itself and exchanges the information with all other adapters. First a decision-making adapter is identified. Then the decision-making adapter compares the adapter-generated information of all the adapters and makes a decision determining the primary adapter. The decision-making adapter communicates the decision to all other adapters. The determined primary adapter assumes a role as the primary adapter and the other adapters assume a role as a secondary adapter.

Abstract: When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented.