Abstract: The invention relates to a telecommunication network having IP packet-supporting capabilities, which includes a load distribution processing function, either centralized or distributed, by means of which a load distribution function may be applied to sets of paths between network nodes or sets of links of network trunks. The load distribution processing function handles different load distribution functions. Each of the different load distribution functions is associated to a different network input unit involved in the load distribution for a set of paths between network nodes or a set of trunk links. The invention also relates to a method of load distribution in a telecommunication network as summarized above.

Abstract: A method for packet reordering in a network processor, including the steps of processing packets, dividing the processed packets into a plurality of tiers and reordering the tiers independently from each other and collecting eligible packets from the plurality of tiers in a collector for forwarding. The method further includes the step of during the processing, determining the nominal packet processing time of each packet. The processed packets are divided into the plurality of tiers depending on the nominal packet processing time.

Abstract: In accordance with at least one embodiment of the present invention, a method and apparatus for scheduling traffic in a communications node is provided. Line cards request communication opportunities from a switch fabric. The switch fabric issues grants for such communication opportunities in response to specific requests. By dynamically adjusting usage of such communication opportunities corresponding to such grants among requests of differing priorities and/or latency criteria, embodiments of the present invention are able to provide increased capacity utilization of switching fabric bandwidth while maximizing adherence to priority requirements and/or latency criteria.

Abstract: A system and method of scheduling and servicing events in a communications network are described. To provide improved efficiency while maintaining fairness to all traffic a two slot dynamic length Weighted Fair Queuing (WFQ) calendar is implemented. The two slot calendar can be transformed to provide fine granularity utilizing a hierarchical WFQ scheme.

Abstract: A method and apparatus for frame-aware and pipelined hierarchical scheduling is described. In accordance with at least one embodiment of the invention, some or all schedulers of a communication node are associated with one or more storage devices that maintain values used by corresponding higher level schedulers to make scheduling decisions. Because of the nature of the scheduling decision flow and the potential to update registers in real-time, the scheduling arrangement can respond almost immediately to changes occurring at the input queues, which allows scheduling to be responsive to differing priorities of incoming cells. The nature of the scheduling decision flow also allows pipelined scheduling, in which scheduling of one or more additional cells can begin before scheduling of a first cell is completed.

Abstract: A method for searching entries in a ternary content addressable memory (“TCAM”) device for one or more matches to an input, comprising: (a) providing a first portion of the input to the TCAM and receiving a first indication from the TCAM as to whether the first portion matches one or more of the entries in the TCAM; and, (b) if the first indication is negative, providing a second portion of the input combined with a hashed version of the first portion to the TCAM and receiving a second indication from the TCAM as to whether the second portion combined with the hashed version of the first portion matches one or more of the entries in the TCAM.

Abstract: A method for searching entries in a ternary content addressable memory (“TCAM”) device for one or more matches to an input, comprising: (a) providing a first portion of the input to the TCAM and receiving a first indication from the TCAM as to whether the first portion matches one or more of the entries in the TCAM; and, (b) if the first indication is negative, providing a second portion of the input combined with a hashed version of the first portion to the TCAM and receiving a second indication from the TCAM as to whether the second portion combined with the hashed version of the first portion matches one or more of the entries in the TCAM.

Abstract: Viewers of video programming are provided with a low effort mechanism to access product or service information related to a program being viewed. This benefits the viewers by providing them with only desired information, and advertisers of the products and services, by focusing their messages on their target market. The availability of advertising or other supplemental information is provided to the viewer within the programming, at places that are time-marked when the programming is being developed or in real time. In response to receiving a request from the viewer for this information, any information associated with the time marker is delivered to the viewer.

Abstract: An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory sections. Sequential parts of the software program are in sequential sections. The software program may have a common portion which is repeated in each of the memory sections. Arbiter logic may control which of the processing units accesses which of the memory sections in each memory access cycle.

Abstract: A fast and scalable pattern making engine is presented. The engine represents variations on a Shift-And method capable of matching patterns in data streams having high speed data rates. In one aspect of the invention high speed is achieved by accessing the pattern RAM in parallel. In another aspect, the input is likened to TDM and individual slots or channels are accessed separately. The two aspects can also be combined to provide a scalable and high speed pattern matching engine. The engine is adaptable to streams of known length or more complex expressions such as regular expressions with arbitrary length.

Abstract: An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory sections. Sequential parts of the software program are in sequential sections. The software program may have a common portion which is repeated in each of the memory sections. Arbiter logic may control which of the processing units accesses which of the memory sections in each memory access cycle.

Abstract: The present invention is related to a method for packet reordering in a network processor (2), comprising the steps of Processing packets, Dividing the processed packets into a plurality of tiers and reordering said tiers independently from each other and collect eligible packets from the plurality of tiers in a collector for forwarding. The method further comprises the step of during the processing, determining the nominal packet processing time of each packet. The processed packets are divided into said plurality of tiers depending on said nominal packet processing time.

Abstract: The method applies to a telecommunication network having IP packet-supporting capabilities when said network includes a load distribution processing function which is either centralized or distributed and by means of which a load distribution function is applied to sets of paths between network nodes and/or sets of links (Lk1, Lkp) of network trunks (12).