Abstract: The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.

Abstract: An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

Abstract: A charge pump has two inputs, each for an input clock signal, and an output for the output of a pumped output potential. Two pumping capacitors are connected to the inputs. Second electrodes of the pumping capacitors are in each case connected via a first circuit module to a supply potential (ground) and via a second circuit module to the output. Also present is a controllable short-circuiting element, the controllable path of which is disposed between the second electrodes of the two pumping capacitors.

Abstract: A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

Abstract: A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.

Abstract: A charge pump has two inputs, each for an input clock signal, and an output for the output of a pumped output potential. Two pumping capacitors are connected to the inputs. Second electrodes of the pumping capacitors are in each case connected via a first circuit module to a supply potential (ground) and via a second circuit module to the output. Also present is a controllable short-circuiting element, the controllable path of which is disposed between the second electrodes of the two pumping capacitors.

Abstract: The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.

Abstract: An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

Abstract: A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

Abstract: A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.

Abstract: A semiconductor memory, in particular a ferroelectric semiconductor memory, has a differential write/read amplifier which is connected, via transfer transistors, to a bit line pair. The bit line pair includes a bit line and a corresponding reference bit line. The differential write/read amplifier is for reading data from and writing data to the memory capacitor (MC). In order to improve the accuracy of the bit line reference voltage, a main reference bit line is connected, via a charge switching element, to a reference voltage. At least one further reference bit line is connected to the main reference bit line via an equalization switching element for charge equalization between the reference bit lines.

Abstract: The memory has a control unit, which, in order to generate a common reference potential on the two bit lines, turns on the first switching element and the selection transistors of the two reference memory cells and, after a specific time period, turns off the selection transistors, while the first switching element remains in the on state and compensates for a potential difference between the two bit lines.

Abstract: The contact spring arrangement has an elongated contact spring having a rigid connecting leg which extends approximately parallel to the contact spring and conducts the switching current in a direction opposite to the contact spring. On the side opposite the connecting leg the contact spring has a contact piece which co-operates with an opposite counter-contact element having a contact piece. The repulsive forces between the connecting leg and the contact spring become so long that even in the case of the highest short circuit currents no welding of the contacts results when in the case of contact pieces made from silver or a silver alloy the length of the gap formed between the contact spring and connecting leg is at least 20 times larger than the average spring spacing in the gap.

Abstract: The invention relates to molded getter bodies for use in encapsulated electrical components. The getter bodies are formable into compressed body shapes in a simplified manner from a mixture of (A) a getter material consisting of activated carbon, zeolite, zirconium and mixtures thereof, (B) polyamide, and (C) polyethylene wax. The molded getter bodies of the invention have improved accuracy as to size, increased getter capacity, and uniform getter activity relative to the prior art.

Abstract: An electrical relay assembly has a spring action bridge contact for engaging with two counter contact elements. The bridge contact is connected with an armature at one end of a longitudinal first section. The other end of the first section is connected to a linearly directed second section having two contact points facing opposite the counter contact elements. The first section has a lateral width not greater than the distance between the contact points. A lever action of the contact points about two different axes thereby results, as a consequence of which a frictional effect is produced at the contact points. The bridge contact is particularly applicable for the switching of low currents.

Abstract: A getter body for use in encapsulated electrical components is of the type consisting of a powder mixture which has been compressed into tablet form. The powder mixture contains in addition to traditional getter material such as activated carbon, zeolite or the like, aluminum stearate and a binder containing a synthetic such as a polyamide. The getter body is produced in several sequential steps. The getter material is mixed with a polycarbonate or a water glass solution, which is then dried and then pulverized. To this first powder is added the aluminum stearate and the binder containing a synthetic. The resulting powder may then be dried and is then pressed into tablets. The tablets may then be heat-cured and are then surfaced polished. The resulting tablets have good abrasion resistance without a noticeable loss in the getter effectiveness.