Patents by Inventor Robert F. CHENEY

Robert F. CHENEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit package lids with polymer features
    Patent number: 11935799
    Abstract: Disclosed herein are integrated circuit (IC) package lids with polymer features, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A foot or rib of the lid may include a polymer material.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Elah Bozorg-Grayeli, Taylor William Gaines, Frederick W. Atadana, Sergio Antonio Chan Arguedas, Robert F. Cheney
  • INTEGRATED CIRCUIT PACKAGE LIDS WITH POLYMER FEATURES
    Publication number: 20200411395
    Abstract: Disclosed herein are integrated circuit (IC) package lids with polymer features, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A foot or rib of the lid may include a polymer material.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Elah Bozorg-Grayeli, Taylor William Gaines, Frederick W. Atadana, Sergio Antonio Chan Arguedas, Robert F. Cheney
  • Method for forming an electrical device and electrical devices
    Patent number: 10269695
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
  • METHOD FOR FORMING AN ELECTRICAL DEVICE AND ELECTRICAL DEVICES
    Publication number: 20170263517
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Method for forming an electrical device and electrical devices
    Patent number: 9691675
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
  • METHOD FOR FORMING AN ELECTRICAL DEVICE AND ELECTRICAL DEVICES
    Publication number: 20170178988
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
  • On Package Floating Metal/Stiffener Grounding to Mitigate RFI and SI Risks
    Publication number: 20160268213
    Abstract: An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Hongjin JIANG, Robert STARKSTON, Digvijay A. RAORANE, Keith D. JONES, Ashish DHALL, Omkar G. KARHADE, Kedar DHANE, Suriyakala RAMALINGAM, Li-Sheng WENG, Robert F. CHENEY, Patrick N. STOVER