Abstract: A method, computer program product, and a computer system are disclosed for processing information using hardware instructions in a processor of a computer system by performing a hardware reduction instruction using an input to calculate at least one range reduction factor of the input; performing a hardware restoration instruction using the input to calculate at least one range restoration factor of the input; and performing a final fused multiply add (FMA) type of hardware instruction or a multiply (FM) hardware instruction by combining an approximation based on a value reduced by the at least one range reduction factor with the at least one range restoration factor.

Abstract: A method is disclosed to simulate operation of a grid structure. The method includes specifying a type of simulation to be performed and at least one initial condition with a user interface of a device such as a mobile device, where the grid structure comprises at least one of a power generation grid and a power distribution grid. The method further includes transmitting the specified type of simulation and the at least one initial condition from the user device to a computing platform; receiving from the computing platform a result of the simulation at the user device; and visualizing the result of the simulation with the user interface. The type of simulation can be an N-k contingency analysis simulation, where k is equal to zero, 1 or greater than 1.

Abstract: A data processing system includes a user interface with a user input configured to enable a user to specify a type of simulation to be performed and at least one initial condition, where the simulation is executed using at least one sensor input from a grid structure composed of at least one of a power transmission and distribution grid. The user interface further has a display configured to visualize a representation of a result of a simulation of at least one scenario by presenting a multi-dimensional representation comprised of indicators, where each indicator corresponds to at least one simulation result. The user interface responds to a selection of one of the indicators by the user to visualize a result of the corresponding simulation. The type of simulation can be an N?k contingency analysis simulation, where k is equal to zero, 1 or greater than 1.

Abstract: A method, computer program product, and a computer system are disclosed for processing information using hardware instructions in a processor of a computer system by performing a hardware reduction instruction using an input to calculate at least one range reduction factor of the input; performing a hardware restoration instruction using the input to calculate at least one range restoration factor of the input; and performing a final fused multiply add (FMA) type of hardware instruction or a multiply (FM) hardware instruction by combining an approximation based on a value reduced by the at least one range reduction factor with the at least one range restoration factor.

Abstract: A method, computer program product, and a computer system are disclosed for processing information using hardware instructions in a processor of a computer system by performing a hardware reduction instruction using an input to calculate at least one range reduction factor of the input; performing a hardware restoration instruction using the input to calculate at least one range restoration factor of the input; and performing a final fused multiply add (FMA) type of hardware instruction or a multiply (FM) hardware instruction by combining an approximation based on a value reduced by the at least one range reduction factor with the at least one range restoration factor.

Abstract: A method, computer program product, and a computer system are disclosed for processing information using hardware instructions in a processor of a computer system by performing a hardware reduction instruction using an input to calculate at least one range reduction factor of the input; performing a hardware restoration instruction using the input to calculate at least one range restoration factor of the input; and performing a final fused multiply add (FMA) type of hardware instruction or a multiply (FM) hardware instruction by combining an approximation based on a value reduced by the at least one range reduction factor with the at least one range restoration factor.

Abstract: A data processing system includes a user interface with a user input configured to enable a user to specify a type of simulation to be performed and at least one initial condition, where the simulation is executed using at least one sensor input from a grid structure composed of at least one of a power transmission and distribution grid. The user interface further has a display configured to visualize a representation of a result of a simulation of at least one scenario by presenting a multi-dimensional representation comprised of indicators, where each indicator corresponds to at least one simulation result. The user interface responds to a selection of one of the indicators by the user to visualize a result of the corresponding simulation. The type of simulation can be an N?k contingency analysis simulation, where k is equal to zero, 1 or greater than 1.

Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.

Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.

Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.

Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.

Abstract: Methods of bit manipulation within a computer processor are disclosed. Improved flexibility in bit manipulation proves helpful in computing elementary functions critical to the performance of many programs and for other applications. In one embodiment, a unit of input data is shifted/rotated and multiple non-contiguous bit fields from the unit of input data are inserted in an output register. In another embodiment, one of two units of input data is optionally shifted or rotated, the two units of input data are partitioned into a plurality of bit fields, bitwise operations are performed on each bit field, and pairs of bit fields are combined with either an AND or an OR bitwise operation. Embodiments are also disclosed to simultaneously perform these processes on multiple units and pairs of units of input data in a Single Input, Multiple Data processing environment capable of performing logical operations on floating point data.

Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.

Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.

Abstract: A method is disclosed to simulate operation of a grid structure. The method includes specifying a type of simulation to be performed and at least one initial condition with a user interface of a device such as a mobile device, where the grid structure comprises at least one of a power generation grid and a power distribution grid. The method further includes transmitting the specified type of simulation and the at least one initial condition from the user device to a computing platform; receiving from the computing platform a result of the simulation at the user device; and visualizing the result of the simulation with the user interface. The type of simulation can be an N-k contingency analysis simulation, where k is equal to zero, 1 or greater than 1.

Abstract: A data processing system includes a user interface with a user input configured to enable a user to specify a type of simulation to be performed and at least one initial condition, where the simulation is executed using at least one sensor input from a grid structure composed of at least one of a power transmission and distribution grid. The user interface further has a display configured to visualize a representation of a result of a simulation of at least one scenario by presenting a multi-dimensional representation comprised of indicators, where each indicator corresponds to at least one simulation result. The user interface responds to a selection of one of the indicators by the user to visualize a result of the corresponding simulation. The type of simulation can be an N?k contingency analysis simulation, where k is equal to zero, 1 or greater than 1.

Abstract: A set of instructions for implementation in a floating-point unit or other computer processor hardware is disclosed herein. In one embodiment, an extended-range fused multiply-add operation, a first look-up operation, and a second look-up operation are each embodied in hardware instructions configured to be operably executed in a processor. These operations are accompanied by a table which provides a set of defined values in response to various function types, supporting the computation of elementary functions such as reciprocal, square, cube, fourth roots and their reciprocals, exponential, and logarithmic functions. By allowing each of these functions to be computed with a hardware instruction, branching and predicated execution may be reduced or eliminated, while also permitting the use of distributed instructions across a number of execution units.

Abstract: Methods of bit manipulation within a computer processor are disclosed. Improved flexibility in bit manipulation proves helpful in computing elementary functions critical to the performance of many programs and for other applications. In one embodiment, a unit of input data is shifted/rotated and multiple non-contiguous bit fields from the unit of input data are inserted in an output register. In another embodiment, one of two units of input data is optionally shifted or rotated, the two units of input data are partitioned into a plurality of bit fields, bitwise operations are performed on each bit field, and pairs of bit fields are combined with either an AND or an OR bitwise operation. Embodiments are also disclosed to simultaneously perform these processes on multiple units and pairs of units of input data in a Single Input, Multiple Data processing environment capable of performing logical operations on floating point data.

Abstract: Enabling application instructions to access mathematical functions from an accelerated function library to perform instructions. In the performance of the instructions, applying a predefined test instruction on a value, the value being at least one of an input argument, an intermediate result or a final result to determine if the value is a general-case or a predetermined special-case. Responsive to a determination that the value is a special-case, performing a predetermined set of special-case instructions for the performance of the mathematical function.

Abstract: A method and arrangements for increased precision in the computation of a reciprocal square root is disclosed. In accordance with the present invention, it is possible to achieve fifty three (53) bits of precision in less processing time than previously possible.