Patents by Inventor Robert F. Krick
Robert F. Krick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130311724Abstract: A cache system includes plurality of first caches at a first level of a cache hierarchy and a second cache at a second level of the cache hierarchy which is lower than the first level of cache hierarchy coupled to each of the plurality of first caches. The second cache enforces a cache line replacement policy in which the second cache selects a cache line for replacement based in part on whether the cache line is present in any of the plurality of first caches and in part on another factor.Type: ApplicationFiled: May 17, 2012Publication date: November 21, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: William L. Walker, Robert F. Krick, Tarun Nakra, Pramod Subramanyan
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Patent number: 7730281Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: GrantFiled: October 17, 2007Date of Patent: June 1, 2010Assignee: Intel CorporationInventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
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Publication number: 20080133894Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: ApplicationFiled: October 17, 2007Publication date: June 5, 2008Inventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
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Patent number: 7334115Abstract: The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.Type: GrantFiled: June 30, 2000Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Reynold V. D'Sa, Alan B. Kyker, Slade A. Morgan, Rebecca E. Hebda, Richard A. Weier, Robert F. Krick
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Patent number: 7321963Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: GrantFiled: February 5, 2004Date of Patent: January 22, 2008Assignee: Intel CorporationInventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
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Patent number: 7114057Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: GrantFiled: October 30, 2001Date of Patent: September 26, 2006Assignee: Intel CorporationInventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
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Patent number: 7032077Abstract: A memory architecture with a multiple cache coherency includes at least one processor with a storage area in communication with a cache memory. A main bus transmits and receives data to and from the cache memory and the processor. A coherency control in communication with the cache memory and the processor is configured to determine an existence or location of data in the cache memory or the storage area in response to a data request from the main bus. The coherency control dispatches an existence or location result to the main bus.Type: GrantFiled: December 23, 2002Date of Patent: April 18, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Paul L. Rogers, Robert F. Krick, Vipul Gandhi
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Patent number: 6950906Abstract: A method of operating a cache comprises the steps of reading first information from a tag memory for at least two cache lines; reading second information from the tag memory for at least two cache lines; writing third information to the tag memory updating the first information; comparing (i) an address of the tag memory associated with the step of reading the second information with (ii) an address of the tag memory associated with the step of writing the third information and, in response, selectively replacing the second information with the third information; and writing, after the step of comparing, fourth information to the tag memory updating the second information.Type: GrantFiled: December 13, 2002Date of Patent: September 27, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert F. Krick, Duane A. Wiens
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Patent number: 6918021Abstract: A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.Type: GrantFiled: April 9, 2002Date of Patent: July 12, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert F. Krick, David Johnson, Paul L. Rogers
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Patent number: 6915396Abstract: The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one outstanding transaction affects the same memory location, dependencies are established to ensure the correct sequencing of the competing transactions. In a preferred embodiment the dependency is configured to ensure that, as each request is inserted, other outstanding requests are checked to determine if the same memory location is accessed. If the same memory location is affected, a dependency is created which ensures the youngest queue entry which is present at the time the check is made occurs before the present outstanding request.Type: GrantFiled: May 10, 2001Date of Patent: July 5, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Duane A Wiens, Robert F. Krick
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Publication number: 20040225867Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: ApplicationFiled: February 5, 2004Publication date: November 11, 2004Inventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
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Publication number: 20040123034Abstract: In representative embodiments, a memory architecture is provided that includes a main bus, at least one CPU, a cache memory that caches the CPU, and a coherency control that determines the existence or location of a data request received from the main bus in the processor or the cache.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Paul L. Rogers, Robert F. Krick, Vipul Gandhl
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Publication number: 20040117558Abstract: A method of operating a cache comprises the steps of reading first information from a tag memory for at least two cache lines; reading second information from the tag memory for at least two cache lines; writing third information to the tag memory updating the first information; comparing (i) an address of the tag memory associated with the step of reading the second information with (ii) an address of the tag memory associated with the step of writing the third information and, in response, selectively replacing the second information with the third information; and writing, after the step of comparing, fourth information to the tag memory updating the second information.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Inventors: Robert F. Krick, Duane A. Wiens
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Publication number: 20040098565Abstract: An instruction pipeline in a microprocessor, comprising a plurality of pipeline units with each of the pipeline units processing instructions. At least one of the plurality of pipeline units receives the instructions from another of the pipeline units, stores the instructions and reissues at least one of the instructions after a stall occurs in the instruction pipeline.Type: ApplicationFiled: June 19, 2003Publication date: May 20, 2004Inventors: Joseph Rohlman, Anil Sabbavarapu, Robert F. Krick
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Patent number: 6711669Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: GrantFiled: January 10, 2003Date of Patent: March 23, 2004Assignee: Intel CorporationInventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
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Publication number: 20030101209Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: ApplicationFiled: January 10, 2003Publication date: May 29, 2003Inventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
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Publication number: 20020188821Abstract: The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one outstanding transaction affects the same memory location, dependencies are established to ensure the correct sequencing of the competing transactions. In a preferred embodiment the dependency is configured to ensure that, as each request is inserted, other outstanding requests are checked to determine if the same memory location is accessed. If the same memory location is affected, a dependency is created which ensures the youngest queue entry which is present at the time the check is made occurs before the present outstanding request.Type: ApplicationFiled: May 10, 2001Publication date: December 12, 2002Inventors: Duane A. Wiens, Robert F. Krick
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Patent number: 6493821Abstract: A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.Type: GrantFiled: June 9, 1998Date of Patent: December 10, 2002Assignee: Intel CorporationInventors: Reynold V. D'Sa, Robert F. Krick, Rebecca E. Hebda, Alan B. Kyker
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Patent number: 6493797Abstract: A method and device are provided for reading data from a trace cache in a manner that reduces the time and power consumed by such an operation. A mini-tag is provided for comparing to a requested address to reduce the amount of data that must be read. Mini-tag read and compare operations may be performed in parallel to a full tag read operation, and a data read operation of only the data identified by a matching mini-tag may be performed in parallel to a full tag compare operation. A victim selection method for writing data into the trace cache is used to maintain the uniqueness of the mini-tags.Type: GrantFiled: March 31, 2000Date of Patent: December 10, 2002Assignee: Intel CorporationInventors: Chan Lee, Richard A. Weier, Robert F. Krick
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Publication number: 20020169931Abstract: A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.Type: ApplicationFiled: April 9, 2002Publication date: November 14, 2002Inventors: Robert F. Krick, David Johnson, Paul L. Rogers