Abstract: According to some embodiments, a method and apparatus are provided to determine a first operating point and a second operating point associated with a graphics processing unit, automatically determine a plurality of voltage/frequency values between the first operating point and the second operating point, and define a plurality of power states of the graphic processing unit. One or more of the power states may be associated with one of the plurality of voltage/frequency values. Each of the plurality of voltage/frequency values may include both a voltage and a frequency.

Abstract: According to some embodiments, a method and apparatus are provided to determine a first operating point and a second operating point associated with a graphics processing unit, automatically determine a plurality of voltage/frequency values between the first operating point and the second operating point, and define a plurality of power states of the graphic processing unit. One or more of the power states may be associated with one of the plurality of voltage/frequency values. Each of the plurality of voltage/frequency values may include both a voltage and a frequency.

Abstract: A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.

Abstract: A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.

Abstract: A computer system includes an apparatus for conserving power in a tag static random access memory (SRAM). The computer system includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The computer system also includes circuitry to power up the tag SRAM out of the reduced power consumption state while maintaining the integrity of the data stored in the tags. The computer system includes a bus, a processor, a cache memory and a memory controller. The memory controller is comprised of a tag static random access memory (SRAM) which includes sense amplifier circuitry and control logic for activating the tag SRAM in response to an address strobe signal (ADS#) from the processor initiating access to the tag SRAM.

Abstract: A method and apparatus for conserving power in a tag SRAM. The present invention includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The present invention also includes circuitry to power up the tag SRAM out of the reduced power consumption state while maintaining the integrity of the data stored in the tags.