Abstract: Location-independent references include a live reference containing a location of a remote object and a universally unique identifier (UUID) which provides a unique global reference to that remote object. If a method call to the remote object using the live reference fails, the UUID is used to obtain a new reference to the remote object and the new reference is then used to make another method call. A new reference can be obtained from an identifier directory that contains a mapping between UUIDs and location-independent references. When a remote object is first created, or when a remote object is moved from one location to another, the remote object registers with any and all such directories that it can find in its environment. These registrations are leased; that is, if they are not occasionally refreshed by the remote object which registered them, they are dropped from the directory.

Abstract: A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as “places” and “paths,” and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.

Abstract: A memory interface is provided between a processor and a memory subsystem which is capable of multiple concurrent transactions or accesses. The interface between the processor and the memory carries read and write operations as well as "barrier" operations, where a barrier operation signals the non-reorderability of operations. In one variation, the memory interface is an interface to one or more memory mapped input/output (I/O) devices or computational devices.

Abstract: In certain systems where a series of stages are employed, it is desirable to control the action of a stage without possibility of interference form adjacent stages. A circuit of linked mutual exclusion elements is described which renders inactive the stages adjacent to an active stage, or inhibits action in a stage if any of its neighbors is active. This ensures that the stages adjacent to an active stage remain inactive, thereby avoiding problems associated with input events changing while an adjacent stage is active.

Abstract: A multi-channel recursive interface having independent channels that can be used in, for example, multi-level memory systems is disclosed. Separate read and write command channels and read and write completion channels permit concurrent read and write operations. A memory system according to the present invention uses a write buffer to resolve read data ambiguity when concurrently reading and writing into the same memory location. With independent and asynchronous read and write channels, the interface of the present invention retains its properties even if separated from the system it interfaces by communication channels exhibiting any latency such as first in first out (FIFO) registers of arbitrary lengths. Such FIFOs can improve the throughput of the communication channels between the interface and the system it interfaces with. The recursive interface can flexibly serve many levels of memory.

Abstract: A counterflow pipeline having a scoreboard table and a register file is disclosed. In the counterflow pipeline, information flows in two directions. Instructions flow up the pipeline during execution. The results from previous instructions flow down the same pipeline. As an instruction meets a result that is needed by that instruction, that result is garnered. The scoreboard table maintains a record of the registers values that are being recomputed in the counterflow pipeline at any given point in time. When a new instruction enters the counterflow pipeline, the register values it needs are compared to the record of register values being recomputed or otherwise stored in the scoreboard table. If a match occurs, the source value is not fetched from the register file. Rather, the needed source value is garnered in the counter flow pipeline. By this procedure, the number of times the register file need be accessed is significantly reduced.

Abstract: A counterflow computing pipeline including a series of similar stages is disclosed. In the basic form of the pipeline, the stages are arranged in a linear fashion and each stage in the pipeline communicates with its two adjacent stages. The flow of data elements in the pipeline is bi-directional. A first data stream of data elements flows in a first direction from stage to stage in the pipeline. A second data stream of data elements flows from stage to stage in the pipeline in a second direction counter to the first direction. Circuitry at each stage is provided so that every data element flowing in the first direction meets each and every data element that it passes flowing in the second direction. According to various embodiments of the invention, when two data elements meet at a stage, circuitry may be provided to compare the data elements, copy data from one data element to the other, or otherwise, cause the data elements to interact.

Abstract: An electronic image processing system includes a controller for receiving character font data from a main memory and for converting it to image data utilizable by a raster output device capable of formatting the image data in a plurality of scan lines onto an imaging medium. The controller includes an input memory coupled to the main memory for receiving character font data therefrom, a data pattern memory for providing a predetermined pattern of data in response to a predetermined address signal, and a plurality of band buffer memories each capable of storing image data representing a predetermined number of scan lines constituting an image band, each band buffer memory having enable input lines and associated data input lines. The input memory is addressed to access character font data therefrom, such accessed character font data being then applied to respective enable input lines of a selected one of the band buffer memories.