Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable wordline signal pulse width which may be reduced sufficiently to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and a nearly error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline signal pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline signal pulse width with an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

Abstract: A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).

Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).

Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

Abstract: Techniques and mechanisms for determining an amount of accommodation for an ophthalmic system are described. In an embodiment, the ophthalmic system includes a first circuit and a second circuit, each comprising a respective photodiode. The second circuit is configured to provide a light response profile that is more linear than a light response profile provided by the first circuit. Light sensing by the first circuit results in generation of a first signal indicating a level of ambient light in a surrounding environment. Other light sensing by the second circuit results in a second signal being generated. An amount of accommodation is determined based at least in part on the second signal.

Abstract: Techniques and mechanisms for determining an amount of accommodation for an ophthalmic system are described. In an embodiment, the ophthalmic system includes a first circuit and a second circuit, each comprising a respective photodiode. The second circuit is configured to provide a light response profile that is more linear than a light response profile provided by the first circuit. Light sensing by the first circuit results in generation of a first signal indicating a level of ambient light in a surrounding environment. Other light sensing by the second circuit results in a second signal being generated. An amount of accommodation is determined based at least in part on the second signal.

Abstract: Techniques and mechanisms for providing access to an accommodation-capable eye-mountable device via a user interface of an auxiliary device. In an embodiment, the user interface provides prompts for a user of the eye-mountable device to perform various viewing actions, where the eye-mountable device receives from the auxiliary device communications indicating respective times of the viewing actions. Based on the communications, the eye-mountable device generates configuration information indicating a correspondence of respective states of the eye-mountable device to respective characteristics of the viewing actions. In another embodiment, operational modes of the eye-mountable device are defined based on the configuration information.

Abstract: Techniques and mechanisms to perform photodetection with an eye-mountable device. In an embodiment, the eye-mountable device includes an enclosure material and light sensor circuitry formed therein, the enclosure material to be disposed in or on an eye of a user. The light sensor circuitry comprises a transimpedance amplifier circuit including a differential amplifier, one or more feedback paths coupled across the differential amplifier, a photodiode and a capacitor coupled between the photodiode and an input terminal of the differential amplifier. Incidence of light upon the photodiode results in some charging of the capacitor, where an amplified signal is provided at an output terminal of differential amplifier based on such charging. The capacitor mitigates static power consumption by the photodiode. In another embodiment, the amplified signal is evaluated based on at least two threshold values to detect a direction of gaze by the user.

Abstract: Techniques and mechanisms to perform photodetection with an eye-mountable device. In an embodiment, the eye-mountable device includes an enclosure material and light sensor circuitry formed therein, the enclosure material to be disposed in or on an eye of a user. The light sensor circuitry comprises a transimpedance amplifier circuit including a differential amplifier, one or more feedback paths coupled across the differential amplifier, a photodiode and a capacitor coupled between the photodiode and an input terminal of the differential amplifier. Incidence of light upon the photodiode results in some charging of the capacitor, where an amplified signal is provided at an output terminal of differential amplifier based on such charging. The capacitor mitigates static power consumption by the photodiode. In another embodiment, the amplified signal is evaluated based on at least two threshold values to detect a direction of gaze by the user.

Abstract: Techniques and mechanisms for providing access to an accommodation-capable eye-mountable device via a user interface of an auxiliary device. In an embodiment, the user interface provides prompts for a user of the eye-mountable device to perform various viewing actions, where the eye-mountable device receives from the auxiliary device communications indicating respective times of the viewing actions. Based on the communications, the eye-mountable device generates configuration information indicating a correspondence of respective states of the eye-mountable device to respective characteristics of the viewing actions. In another embodiment, operational modes of the eye-mountable device are defined based on the configuration information.