Abstract: Embodiments provide an Energy Reduction Maintenance Setting (ERMS) key that includes a data connector configured to communicatively couple to a data port of a target device. The ERMS key further includes an illumination device and an actuator mechanism having a base positional state and an actuated positional state. The ERMS key includes logic configured to, upon detecting the actuator mechanism has moved from the base positional state to the actuated positional state, generate and transmit a first data message to the target device through the data connector instructing the target device to enter a protected mode. The logic is further configured to, upon receiving a second data message from the target device over the data connector acknowledging that the target device has successfully entered the protected mode, cause the illumination device to illuminate.

Abstract: Embodiments provide an Energy Reduction Maintenance Setting (ERMS) key that includes a data connector configured to communicatively couple to a data port of a target device. The ERMS key further includes an illumination device and an actuator mechanism having a base positional state and an actuated positional state. The ERMS key includes logic configured to, upon detecting the actuator mechanism has moved from the base positional state to the actuated positional state, generate and transmit a first data message to the target device through the data connector instructing the target device to enter a protected mode. The logic is further configured to, upon receiving a second data message from the target device over the data connector acknowledging that the target device has successfully entered the protected mode, cause the illumination device to illuminate.

Abstract: A plug-on neutral (PON) device includes a housing that defines a phase cooperation portion configured to physically cooperate with phase buses of a bus assembly. The phase cooperation portion is configured to be electrically isolated from the phase buses and stabilize the PON device when installed on the bus assembly. A neutral cooperation portion is configured to physically cooperate with the neutral bus and to physically stabilize the PON device when installed. An electrical connector disposed at the neutral cooperation portion is configured to electrically connect to the neutral bus at an external end and to electrically connect to a conductive current path at its internal end. A lug assembly has one or more conductive terminal lugs, each terminal lug configured to receive current from an external neutral source via an aperture in the lug end of the housing and to electrically connect to the current path.

Abstract: Embodiments provide an Energy Reduction Maintenance Setting (ERMS) key that includes a data connector configured to communicatively couple to a data port of a target device. The ERMS key further includes an illumination device and an actuator mechanism having a base positional state and an actuated positional state. The ERMS key includes logic configured to, upon detecting the actuator mechanism has moved from the base positional state to the actuated positional state, generate and transmit a first data message to the target device through the data connector instructing the target device to enter a protected mode. The logic is further configured to, upon receiving a second data message from the target device over the data connector acknowledging that the target device as successfully entered the protected mode, cause the illumination device to illuminate.

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Abstract: A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.

Abstract: In an electrical distribution cabinet a mechanism providing quick, reliable, passive arc blast control has a flue chamber surrounding the likely arc site such as an electrical connection point. The flue chamber provides a flue channel which lengthens the arc and attenuates the current and temperature until the arc is extinguished. Preferably, the flue chamber and channel are formed of opposable open-faced polyhedral structures, one fitting inside the other. The mechanism is particularly suited for draw-out circuit breaker connections in a switch gear cabinet.

Abstract: A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure, such as a table, to a non-volatile memory, such as a NAND flash memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure. One or more segments of the logical to physical address mapping structure may be cached in volatile memory, and a size of each segment may be the same as or a multiple of a page size of the NAND flash memory. A lookup or segment table may be provided to indicate a location of each segment and may be optimized for sequential physical addresses.

Abstract: A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.

Abstract: In an electrical distribution cabinet a mechanism providing quick, reliable, passive arc blast control has a flue chamber surrounding the likely arc site such as an electrical connection point. The flue chamber provides a flue channel which lengthens the arc and attenuates the current and temperature until the arc is extinguished. Preferably, the flue chamber and channel are formed of opposable open-faced polyhedral structures, one fitting inside the other. The mechanism is particularly suited for draw-out circuit breaker connections in a switch gear cabinet.

Abstract: A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention.

Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Abstract: In one embodiment, the present invention includes a method for maintaining a sequence of writes into a disk cache, where the writes correspond to disk write requests stored in the disk cache, and ordering cache writes from the disk cache to a disk drive according to the sequence of writes. In this way, write ordering from an operating system to a disk subsystem is maintained. Other embodiments are described and claimed.

Abstract: Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.

Abstract: The above-described methods and computer system describe the use of dynamic addressing, lazy relocations and erases, and page state information to provide fast disk caching and solid state disk applications using solid-state nonvolatile memories. The approach reduces write-latencies for demand requests, as well as the number of erase cycles on erase blocks.

Abstract: An apparatus and method to reduce the initialization time of a system is disclosed. In one embodiment, upon a cache line update, metadata associated with the cache line is stored in a distributed format in non-volatile memory with its associated cache line. Upon indication of an expected shut down, metadata is copied from volatile memory and stored in non-volatile memory in a packed format. In the packed format, multiple metadata associated with multiple cache lines are stored together in, for example, a single memory block. Thus, upon system power up, if the system was shut down in an expected manner, metadata may be restored in volatile memory from the metadata stored in the packed format, with a significantly reduced boot time over restoring metadata from the metadata stored in the distributed format.

Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

Abstract: Briefly, a speculative write back to a memory location is performed when reading a memory word from a destructive read memory. The speculative write back is performed prior to checking the memory word read for errors. Upon detecting an error in the memory word, the memory location is erased and a corrective write back is performed.