Patents by Inventor Robert Feather

Robert Feather has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200050857
    Abstract: A system, method, or web application for providing augmented reality. There is: imaging, using a user interface device operating a mobile web application, a plurality of frame-shaped augmented reality markers within a set of markers, each having an identifier that is unique within the set of markers, thereby generating set unique marker images; generating a plurality of marker templates with stored associated data; automatically identifying the specific frame-shaped augmented reality marker when imaged by its identifier via the mobile web application; automatically displaying data associated with the specific frame-shaped augmented reality marker on an augmented reality display wherein the data displayed is registered three-dimensionally with the specific frame-shaped augmented reality marker, wherein the frame-shaped augmented reality markers include machine-readable orientation information displayed thereon.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 13, 2020
    Applicant: Verascan, Inc.
    Inventors: Fernando Giuseppe Anello, Cameron Robert Feather
  • Patent number: 7376872
    Abstract: Method and apparatus for the testing of embedded memories in integrated circuits such as programmable logic devices are disclosed. In conjunction with a partial BIST engine, an external tester provides the embedded memories with test vectors. The on-chip partial BIST engine retrieves the test vectors from the embedded memories and compares them to corresponding expected test vectors supplied by the external tester. Based upon the comparison, the on-chip partial BIST engine forms comparison results indicating whether the retrieved test vectors differ from the corresponding expected test vectors. For programmable logic devices, a full BIST engine may be configured in the integrated circuit for generating the test vectors on chip.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: May 20, 2008
    Assignee: Lattice Semiconductor Corporation
    Inventors: Michael Nelson, Robert Feather, Hemanshu Vernenker