Abstract: A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in the imaging properties of the main structures which are disposed at an edge of a region containing a multiplicity of main structures. In particular, constrictions at the structures can be significantly reduced or completely avoided and/or a so-called “tilting” of the structures under non-optimum focus conditions is significantly reduced or completely avoided.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: A printed circuit board system includes a printed circuit board device having a multiple access signal line. A plurality of semiconductor apparatuses are arranged on the printed circuit board device. Each semiconductor apparatus includes a signal connection point to be connected to the multiple access signal line; and a signal transmission device for controlling presence of an output signal at the signal connection point.

Abstract: It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage. Therefore, semiconductor circuits having transistors with different operating voltages are provided with transistors having gate oxides of different thicknesses. This allows the gate oxide thickness to be influenced even more extensively. In this case, account is taken of the fact that infrequently addressed transistors, in particular memory transistors given the same gate oxide thickness, have a significantly longer lifetime than frequently switched transistors. An integrated semiconductor circuit having transistors whose gate oxide thicknesses are adapted to the switching frequency having different magnitudes, is proposed.

Abstract: In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multiplicity of data terminals arranged in at least two columns and connected to the pads by data connections. The data connections are configured such that each data connection has essentially the same electrical properties as any other data connection.

Abstract: An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A controllable frequency generator serves for setting a refresh frequency. A temperature sensor circuit detects a temperature of the memory and outputs a first reference value, and an externally writable circuit is provided for outputting a second reference value. The temperature sensor circuit and the externally writable circuit are alternatively connectible to the control input of the frequency generator for setting the refresh frequency. If the externally writable circuit has been written, the second reference value, which corresponds to a temperature, is fed to the frequency generator; otherwise, the first reference value is supplied. In this manner, users of the memory that are unable to measure temperature can expediently optimize the power consumption that is necessary for standby mode and reduce it at low temperatures.

Abstract: The volatile semiconductor memory is constructed from a plurality of memory segments. The information stored in the memory cells must be regularly reconditioned. Here, the time interval after the expiry of which the memory contents of the memory cells are reconditioned is set individually for each memory segment using corresponding subcircuits. The subcircuits receive, in a cyclical sequence, a refresh instruction. The passing on of the refresh instruction to the respective memory segment is interrupted if the segment-specific refresh time has not yet expired. This method of driving is implemented very easily and in a space-saving and cost-effective way in terms of circuitry.

Abstract: An integrated memory having a memory cell array has a control circuit for controlling a memory access for reading out or writing a data signal of one of the memory cells. The control circuit receives, for a memory access, an access command in the form of an activation command, a read command or a write command. Furthermore, the control circuit is designed and can be operated in such a way that, for a memory access, a configuration value for a CAS latency and/or a configuration value for specifying a burst access is received in a combined manner with the access command. As a result, a mode register and a corresponding programming step for programming the register can be eliminated.

Abstract: In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

Abstract: An integrated memory has a plurality of memory cell arrays. The memory cell arrays are in each case assigned a decoder for selecting bit lines and word lines. In order to trigger an access cycle for a memory cell access, a write command or a read command with an active state is generated. Within the access cycle, under the control of a control circuit, respective decoders of the memory cell arrays are driven and data of each of the memory cell arrays are successively read out or written in for as long as the read command or write command remains in the active state. As a result, it is possible to set a comparatively large variable burst length of the memory. A method for operating an integrated memory is also provided.

Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

Abstract: What is specified is an integrated memory having a plurality of memory cell arrays that are each assigned row decoders and column decoders. During read or write operations in the present integrated memory, in each case at least two word lines are activated simultaneously, in each case only one bit line being selected simultaneously. Compared with conventional memory architectures, this results in a high data rate even at very high frequencies and with a variable burst length, and additionally in a comparatively low power loss.

Abstract: The data memory device has a plurality of memory cells for storing data which are represented by a first physical value of the storing memory elements, especially their conductivity or charge. The memory elements are, for example, storage capacitors. A detection device detects the first physical value representing the data and a second detection device is provided for detecting a second physical value of the storage cells or constituents of the same, especially of the storage element, especially the leakage current of the storage capacitor provided for storing the data. The second physical value represents a second detectable item of information in addition to the first physical value representing the data, independently of the first physical value. The invention also relates to a method for permanently storing information in storage cells of a data storage device for reversibly or permanently storing data.

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

Abstract: The voltage regulating circuit, in particular for semiconductor memories, has a reference-voltage generator for generating a reference voltage, an in-phase element for providing a regulated voltage, and an error amplifier for forming a control loop. The in-phase element has a plurality of transistors which are permanently connected to one another on the control side and the load terminals of which are disconnectably connected, in dependence on the required drive strength, to a terminal that outputs the regulated voltage. The voltage regulating circuit is particularly suitable for supplying the voltage for embedded DRAM memories with an application-dependent storage capacity.

Abstract: An integrated semiconductor chip is connected to external terminals with all of its data-carrying bonding pads. One of a plurality of possible data input/data output organizational forms is preset for a normal mode. Not all of the data-carrying bonding pads are used for the normal mode. During a test mode all of the data-carrying bonding pads are used. Thus, irrespective of the preset data input/data output organizational form, a uniform test mode requiring a minimal expenditure of time is possible. A method for controlling a semiconductor chip is also provided.

Abstract: An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A controllable frequency generator serves for setting a refresh frequency. A temperature sensor circuit detects a temperature of the memory and outputs a first reference value, and an externally writable circuit is provided for outputting a second reference value. The temperature sensor circuit and the externally writable circuit are alternatively connectible to the control input of the frequency generator for setting the refresh frequency. If the externally writable circuit has been written, the second reference value, which corresponds to a temperature, is fed to the frequency generator; otherwise, the first reference value is supplied. In this manner, users of the memory that are unable to measure temperature can expediently optimize the power consumption that is necessary for standby mode and reduce it at low temperatures.

Abstract: A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in the imaging properties of the main structures which are disposed at an edge of a region containing a multiplicity of main structures. In particular, constrictions at the structures can be significantly reduced or completely avoided and/or a so-called “tilting” of the structures under non-optimum focus conditions is significantly reduced or completely avoided.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: A printed circuit board system includes a printed circuit board device having a multiple access signal line. A plurality of semiconductor apparatuses are arranged on the printed circuit board device. Each semiconductor apparatus includes a signal connection point to be connected to the multiple access signal line; and a signal transmission device for controlling presence of an output signal at the signal connection point.