Patents by Inventor Robert Floyd Payne
Robert Floyd Payne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10033365Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: May 18, 2017Date of Patent: July 24, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
-
Patent number: 10018576Abstract: A dielectric waveguide (DWG) may be used to identify a composition of a material that is in contact with the DWG. A radio frequency (RF) signal is transmitted into a dielectric waveguide located in contact with the material. The RF signal is received after it passes through the DWG. An insertion loss of the DWG is determined. The presence of the material may be inferred when the insertion loss exceeds a threshold value. The composition of the material may be inferred based on a correlation with the insertion loss. Alternatively, a volume of the material may be inferred based on a correlation with the insertion loss.Type: GrantFiled: December 30, 2014Date of Patent: July 10, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Juan Alejandro Herbsommer, Robert Floyd Payne
-
Patent number: 10014899Abstract: In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.Type: GrantFiled: July 15, 2016Date of Patent: July 3, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert Floyd Payne, Lambert Jacob Helleman
-
Patent number: 9942066Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.Type: GrantFiled: June 27, 2017Date of Patent: April 10, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert Floyd Payne
-
Publication number: 20180095494Abstract: A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.Type: ApplicationFiled: December 6, 2017Publication date: April 5, 2018Inventor: Robert Floyd Payne
-
Publication number: 20180097611Abstract: A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.Type: ApplicationFiled: December 6, 2017Publication date: April 5, 2018Inventor: Robert Floyd Payne
-
Patent number: 9876630Abstract: A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.Type: GrantFiled: December 22, 2015Date of Patent: January 23, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert Floyd Payne
-
Publication number: 20180019781Abstract: In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Applicant: Texas Instruments IncorporatedInventors: ROBERT FLOYD PAYNE, LAMBERT JACOB HELLEMAN
-
Patent number: 9864398Abstract: A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.Type: GrantFiled: December 30, 2015Date of Patent: January 9, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert Floyd Payne
-
Publication number: 20170295045Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.Type: ApplicationFiled: June 27, 2017Publication date: October 12, 2017Inventor: Robert Floyd Payne
-
Patent number: 9780768Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: October 30, 2015Date of Patent: October 3, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
-
Publication number: 20170271736Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.Type: ApplicationFiled: June 6, 2017Publication date: September 21, 2017Inventors: Robert Floyd Payne, Gerd Schuppener, Juan Alejandro Herbsommer
-
Publication number: 20170257087Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
-
Patent number: 9722824Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.Type: GrantFiled: December 30, 2015Date of Patent: August 1, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert Floyd Payne
-
Patent number: 9711837Abstract: A multichannel dielectric wave guide includes a set of dielectric core members that have a length and a cross section shape that is approximately rectangular, The core members have a first dielectric constant value. A cladding surrounds the set of dielectric core members and has a second dielectric constant value that is lower than the first dielectric constant.Type: GrantFiled: April 2, 2013Date of Patent: July 18, 2017Assignee: Texas Instruments IncorporatedInventors: Robert Floyd Payne, Juan Alejandro Herbsommer, Gerd Schuppener
-
Patent number: 9705174Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.Type: GrantFiled: November 26, 2014Date of Patent: July 11, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert Floyd Payne, Gerd Schuppener, Juan Alejandro Herbsommer
-
Publication number: 20170192449Abstract: A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventor: Robert Floyd Payne
-
Publication number: 20170195148Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventor: Robert Floyd Payne
-
Patent number: 9692102Abstract: A dielectric waveguide socket is provided with a dielectric waveguide (DWG) stub having a dielectric core member surrounded by dielectric cladding, the DWG stub having an interface end and an opposite mating end. A socket body is coupled to the DWG stub, such that a mounting surface of the socket body is configured to mount the socket body on a substrate such that the core member of DWG stub forms an angle of inclination with the substrate. The socket body is configured to couple with the end of a DWG cable, such that the end of the DWG cable is held in alignment with the mating end of the DWG stub.Type: GrantFiled: September 25, 2015Date of Patent: June 27, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Juan Alejandro Herbsommer, Robert Floyd Payne
-
Publication number: 20170180113Abstract: A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventor: Robert Floyd Payne