Patents by Inventor Robert Francis Cook

Robert Francis Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6171873
    Abstract: A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: January 9, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ronald Lee Mendelson, Robert Francis Cook, David Frederick Diefenderfer, Eric Gerhard Liniger, John M. Blondin, Donald W. Brouillette
  • Patent number: 6022791
    Abstract: A serpentine pattern has been found to be effective at interrupting propagation of delamination cracks in thin film layers. The ring is provided on a semiconductor chip to suppress crack propagation from the chip edge. The ring is effective even though it is filled with metal, the serpentine pattern providing significantly increased area as compared with a standard linear crack stop that the energy for crack propagation is dissipated. In addition to serpentines, pattern features such as staggered filled ring patterns and connected rings will also be effective at reducing the propagation of delamination cracks from edge to active area by virtue of the increased area of interaction between the crack and the crack stop.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: February 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: Robert Francis Cook, Eric Gerhard Liniger, Ronald Lee Mendelson, Richard Charles Whiteside
  • Patent number: 5953627
    Abstract: The invention relates to a process for making an integrated circuit device comprising (I) a substrate, (ii) metallic circuit lines positioned on the substrate, and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises the condensation product of silsesquioxane precursor in the presence of an organic amine having a boiling point greater than 150.degree. C.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: September 14, 1999
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Raymond Carter, Robert Francis Cook, Martha Alyne Harbison, Craig Jon Hawker, James Lupton Hedrick, Sung-Mog Kim, Eric Gerhard Liniger, Robert Dennis Miller, Willi Volksen, Do Yeung Yoon
  • Patent number: 5888838
    Abstract: A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: March 30, 1999
    Assignee: International Business Machines Corporation
    Inventors: Ronald Lee Mendelson, Robert Francis Cook, David Frederick Diefenderfer, Eric Gerhard Liniger, John M. Blondin, Donald W. Brouillette