Abstract: An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Abstract: An interface includes an enclosure having a plurality of walls interconnected to form a parallelepiped having a space therein. The enclosure is positionable to occupy a plurality of slots located in a computer housing of a first type computer. The enclosure has a width corresponding essentially to a total width of the plurality of slots. The interface further includes a computer subsystem of a second type computer disposed within the space of the enclosure. The computer subsystem includes a circuit card, and a distribution card attached to, and electrically coupled with, the circuit card. The distribution card is connectable to a backplane of the first type computer located external to the enclosure and within the computer housing.

Abstract: A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays—on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.

Abstract: A method and apparatus for reducing the software overhead of message passing in parallel systems. Special purpose hardware assists in constructing each data message sent through a network. Message passing systems generally require that every message be prefixed with a message header describing the key control parameters of the message. The software task is to construct the message header for every message individually and to transmit the header prefixed to every message. The software is relieved of constructing the message header and uses special purpose hardware to accomplish the job more efficiently.

Abstract: A method and hardware apparatus provide a fault tolerant and flexible multi-stage network addressing scheme for transmitting a message with a header containing control bits for selecting from various destination checking functions to be performed. Upon arrival of the message at a node, destination checking is performed or not in response to the massage's header. If destination checking is not performed, or if destination checking is performed and indicates that the node is the desired destination for the message, the message is accepted. If destination checking is performed and indicates that the node is not the desired destination for the message, the message is rejected. Destination checking is disabled during address assignment, broadcasting and multi-casting, and replaced with one's complement-based verification of the sending node.

Abstract: A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.