Abstract: An encryption circuit for receiving an input of a first digital key and plaintext data, the encryption circuit for mathematically manipulating the digital key and the plaintext data to encrypt the plaintext data into encrypted data, wherein at least a portion of the encryption circuit comprises IBG circuitry.

Abstract: A ROM circuit includes a first N channel transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level when a P channel circuit is connected to the first N channel transistor; a pass transistor connected between the output and a data bus, the pass transistor connected to a word line, the word line adapted to turn ON the pass transistor when the word line is asserted; and the P channel circuit connected to the data bus and adapted to provide leakage current to charge a gate in the first N channel transistor when pass transistor is turned ON.

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.