Patents by Inventor Robert G. Blankenship

Robert G. Blankenship has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190220420
    Abstract: Examples may include techniques to enable cache coherency of objects in a distributed shared memory (DSM) system, even where multiple nodes in the system manage the objects. Node memory space includes a tracking address space (TAS) where lines in the TAS correspond to objects in the (DSM). Access to the objects and the TAS is managed by a host fabric interface (HFI) caching agent in HFI of a node.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 18, 2019
    Applicant: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Robert G. Blankenship, Raj K. Ramanujan
  • Publication number: 20190196968
    Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Carl J. Beckmann, Robert G. Blankenship, Chyi-Chang Miao, Chitra Natarajan, Anthony-Trung D. Nguyen
  • Publication number: 20190188178
    Abstract: Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
    Type: Application
    Filed: September 17, 2018
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Debendra Das Sharma
  • Patent number: 10320710
    Abstract: Methods, apparatus, and systems for reliable replication mechanisms based on active-passive HFI protocols build on top of non-reliable multicast fabric implementations. Under a first hardware-based scheme, a reliable replication mechanism is (primarily) implemented via Host Fabric Interfaces (HFIs) coupled to (or integrated in) nodes coupled to a non-reliable fabric. Under this approach, the HFIs take an active role in ensuring reliable delivery of multicast messages to each of multiple target nodes. Under a second hybrid software/hardware scheme, software running on nodes is responsible for determining whether target nodes have confirmed delivery of multicast messages and sending retry messages for cases in which delivery is not acknowledged within a timeout period. At the same time, the HFIs on the target nodes are responsible for generating reply messages containing acknowledgements rather than software running on the target nodes.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Charles A. Giefer, Raj K. Ramanujan, Robert G. Blankenship, Narayan Ranganathan
  • Patent number: 10310978
    Abstract: An apparatus and method for multi-level cache request tracking.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Robert G. Blankenship, Samantika S. Sury
  • Patent number: 10268583
    Abstract: A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Robert Beers, Robert G. Blankenship, Robert J. Safranek, Jeff Willey, Robert A. Maddox, Aaron T. Spink
  • Publication number: 20190102300
    Abstract: An apparatus and method for multi-level cache request tracking.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: ROBERT G. BLANKENSHIP, SAMANTIKA S. SURY
  • Publication number: 20190102295
    Abstract: A method for adaptively performing a set of data transfer processes in a multi-core processor is described. The method may include receiving, by a shared cache from a first core cache, a first request for a cache line; determining, by the shared cache in response to receipt of the first request, whether the cache line is a widely-shared cache line or a single-producer-single-consumer cache line; and performing, by the first core cache and a second core cache, a three-hop data transfer process in response to determining that the cache line is a single-producer-single-consumer cache line, wherein the three-hop data transfer process transfers the cache line directly from the second core cache to the first core cache.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Samantika S. Sury, Robert G. Blankenship, Simon C. Steely, JR., Yen-Cheng Liu
  • Patent number: 10248591
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 10248325
    Abstract: Memory is to store cache lines, where the cache lines include data and directory information to indicate a directory state of the corresponding cache line. A command is received from a processor over a link, the command including an address. The address is determined to correspond to a particular cache line and the particular cache line is identified to have a particular directory state from the corresponding directory information of the particular cache line. A type of the command is identified and a determination is made that that the directory state of the particular cache line is to change from the particular state to a new state based on the type of the command. The directory information of the particular cache line is changed to reflect the new state and a response is generated to the command.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventor: Robert G. Blankenship
  • Publication number: 20190087240
    Abstract: In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory request and a second memory request; determine whether the second memory request is in contention with the first memory request; and in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol. Other embodiments are described and claimed.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Inventors: Samantika S. Sury, Robert G. Blankenship, Simon C. Steely, JR.
  • Patent number: 10204064
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Patent number: 10198379
    Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson
  • Publication number: 20190004958
    Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship, Vedaraman Geetha, Shrikant M. Shah, Marshall A. Millier, Raanan Sade, Binh Q. Pham, Olivier Serres, Chyi-Chang Miao, Christopher B. Wilkerson
  • Publication number: 20180373632
    Abstract: An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.
    Type: Application
    Filed: August 6, 2018
    Publication date: December 27, 2018
    Inventors: Christopher WILKERSON, Ren WANG, Antoine KAUFMANN, Anil VASUDEVAN, Robert G. BLANKENSHIP, Venkata KRISHNAN, Tsung-Yuan C. Tai
  • Patent number: 10146733
    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
  • Patent number: 10146690
    Abstract: In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory request and a second memory request; determine whether the second memory request is in contention with the first memory request; and in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Samantika S. Sury, Robert G. Blankenship, Simon C. Steely, Jr.
  • Patent number: 10140213
    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Robert G. Blankenship, Jeffrey D. Chamberlain, Yen-Cheng Liu, Vedaraman Geetha
  • Patent number: 10140240
    Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson
  • Publication number: 20180300275
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Application
    Filed: November 22, 2017
    Publication date: October 18, 2018
    Applicant: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek