Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.

Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.

Abstract: Techniques to broadcast a message across a point-to-point network are described. More particularly, some embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. Other embodiments are also disclosed.

Abstract: A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.

Abstract: In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.

Abstract: In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.

Abstract: A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.

Abstract: A cache coherency arrangement to enhance an upbound path for input-output interfaces is disclosed. Several embodiments may enhance upbound write bandwidth and buffer utilization. Some embodiments may comprise requesting content of a memory granule and merging the content with data associated with a write request for the memory granule prior to satisfaction of an ordering rule associated with the write request. Many embodiments may comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation and/or deadlock of transactions or of an input-output interface for transactions. Such embodiments may also comprise invalidating merged content of the memory granule. Further embodiments may comprise reverting the merged content to the data associated with the write request.

Abstract: Embodiments of the invention may monitor or manage the number of retries sent to a node by reserving an entry or path to an outbound port when the node is starved. Some embodiments associate a number of retries with a node in a buffer. Several embodiments compare the number of retries associated with the node against a retry limit to trigger reservation of an entry in a queue. Many embodiments may reserve the entry after the number of retries reaches or surpasses the retry limit. Further embodiments provide a count controller to count the number of retries and a retry controller, responsive to the count controller, to reserve a path to an outbound port. Other embodiments prevent transactions from one node from transmitting to an outbound port via a reserved path when the number of retries for another node is near or approaches the retry limit.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: A cache coherency arrangement to enhance an upbound path for input-output interfaces is disclosed. Several embodiments may enhance upbound write bandwidth and buffer utilization. Some embodiments may comprise requesting content of a memory granule and merging the content with data associated with a write request for the memory granule prior to satisfaction of an ordering rule associated with the write request. Many embodiments may comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation and/or deadlock of transactions or of an input-output interface for transactions. Such embodiments may also comprise invalidating merged content of the memory granule. Further embodiments may comprise reverting the merged content to the data associated with the write request.

Abstract: A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.