Abstract: A combination biomass harvester and baler, in some embodiments, can include a self-propelled vehicle base, an engine compartment, a fuel and radiator compartment, a movement mechanism operably connected to the self-propelled vehicle base, a cutting head assembly, a transfer assembly, and a baler assembly. The baler assembly may be configured to consolidate the biomass into one or more bales. A bale carrying platform is provided to store the bales while the combination biomass harvester and baler continues to move.

Abstract: The present disclosure relates to a combination biomass harvester and baler. In some embodiments, the combination biomass harvest and baler includes a self-propelled vehicle base, an engine compartment, a fuel and radiator compartment, a movement mechanism operably connected to the self-propelled vehicle base, a cutting head assembly, a transfer assembly, and a baler assembly. The baler assembly may be configured to consolidate the biomass into one or more bales. A bale carrying platform is provided to store the bales while the combination biomass harvester and baler continues to move.

Abstract: A method which includes segmenting the content of a document into one or more original document structures, determining which of the one or more original document structures are to be localized, replacing the original document structures to be localized with new content, and automatically adjusting the layout of the document with new content to generate a more aesthetically pleasing document.

Abstract: Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A plurality of interfaces, referred to as switches, together with the agents of the cells, connects the cells together. A clock source provides a clock to a switch, which replicates the clock and provides the replicated clocks to its ports. Each port of the switch, receiving a replicated clock, encodes this replicated clock and sends it over a link to each agent of a cell. Each agent of the cells, receiving an encoded clock, decodes this encoded clock, resulting in a decoded, or an extracted, clock. The agent then replicates the extracted clock and provides the replicates of the extracted clock to a plurality of CPUs of the cell. As a result, CPUs in all cells of the system receive clocks that all are synchronized to the clock provided by the clock source.

Abstract: Embodiments of the invention relate to synchronizing registers. An embodiment includes a plurality of processing cells each includes a plurality of CPUs, which run at different frequencies and each of which has an ar.itc timer register. A CPU in the fastest cell of the plurality of cells is referred to as the fast CPU. CPUs in slower cells are referred to as slow CPUs. At predetermined time intervals, slow CPUs are provided with the ar.itc value of the fast CPU to replace the values of their ar.itc. As a result, values in the ar.itc registers are synchronized without providing negative time. Other embodiments are also disclosed.

Abstract: An apparatus in one example comprises a card guide that provides an installation path for an extension circuit card. The installation path promotes a coupled relationship between the extension circuit card and a circuit board. The card guide comprises a first connector and a second connector. To form the coupled relationship the extension circuit card attaches to one of the first connector and the second connector based on a configuration of the extension circuit card.

Abstract: An apparatus in one example comprises a card guide that provides an installation path for an extension circuit card. The installation path promotes a coupled relationship between the extension circuit card and a circuit board. The card guide comprises a first connector and a second connector. To form the coupled relationship the extension circuit card attaches to one of the first connector and the second connector based on a configuration of the extension circuit card.

Abstract: The present invention includes an integrated circuit that is operable to connect a redundant array of inexpensive disks (RAID) or other peripheral device to a disk controller, such as a small computer system interface (SCSI) controller in a host device. The integrated circuit provides the peripheral device with sole access to the disk controller when operating in a straight mode. In straight mode, the peripheral device may communicate with the disk controller through a PCI bus to perform operations, such as retrieving or writing data to the peripheral device. Also, when in straight mode, other controllers, including the host's CPU, may be prevented from using the disk controller to avoid data collisions, data loss and possible system failure. The integrated circuit may also function in standard mode, such that other controllers connected to the host may access the disk controller.

Abstract: A method and apparatus for assigning interrupts to devices on a PCI bus in a computer system in which a plurality of address lines are channeled through a multiplexer to a PCI device on the PCI bus. The multiplexer enables the user to dynamically select which address line is routed to the IDSEL pin on the PCI device. According to the PCI specification, the address line connected to the IDSEL pin determines the Device ID for that PCI device. In turn, the Device ID establishes which of the four available interrupt INT# lines are assigned to that PCI device. Thus, the interrupt INT# line assignments can be dynamically controlled. Where desired, the user can force two PCI devices to share an interrupt line, or the user can force the devices to use separate interrupts.

Abstract: An integrated circuit package for electrically interconnecting a first bus signal path disposed on a printed circuit board and a second bus signal path disposed on the printed circuit board. The integrated circuit package may have a substrate, an integrated circuit chip die supported by the substrate. The interconnection network may be for electrically connecting the first bus signal path and the second bus signal path to a chip pad on the chip die. Thus, the first bus signal path and the second bus signal path may be electrically interconnected by only the interconnection circuit.

Abstract: A receptacle and cover assembly for collecting lawn debris and the like and including structure for assisting transfer of compacted contents of the receptacle to expendable lawn trash bags and the like, comprising a main receptacle body section in the shape of an upwardly opening container having a skirt-like lower edge formation at the bottom of the receptacle body section for supporting it in upright position, and a removable cover member for the receptacle body section. The body section has a centrally open outer bottom wall portion extending inwardly from the side wall at a position spaced slightly above the lower edge formation providing a shelf-like ledge extending inwardly from the side wall, and a moveable bottom panel member forming a discharge assist piston which rests on shelf-like ledge formation and collectively therewith forms the bottom of the receptacle.

Abstract: The knitting needle is provided with a hook which is so shaped that in lateral cross-section more of the hook wire than usual is located near the inner periphery of the hook bend so as to decrease the maximum stress levels generated in the hook when compared to conventional needle hooks.