Abstract: A fault tolerant error correction circuit utilizing any modified Hamming code is disclosed. In addition to correcting single bit errors and detecting double bit errors, the error correction circuit disclosed can tolerate the failure of any single parity check subcircuit without corrupting the information bits of a correct input data pattern. Improved reliability results because a using system will remain UP if there is a single bit error in the input data pattern or faults in a single parity check subcircuit, but not both. If both an error and a fault do occur, the error correction circuit will either report a double bit error or a correct output will be generated with no error indication.