Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits the flow of current through the NAND gate and a portion of the OAI gate to which the controller is connected. As a consequence, leakage power is not consumed within the multiplexer. Several of the applications in which the circuit is used are also demonstrated in the specification.

Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.

Abstract: A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits the flow of current through the NAND gate and a portion of the OAI gate to which the controller is connected. As a consequence, leakage power is not consumed within the multiplexer. Several of the applications in which the circuit is used are also demonstrated in the specification.

Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.

Abstract: An improved method and process is provided for verifying a digital logic design complies with certain manufacturing test rules or guidelines. A replacement is created for any portion of a design to make it usable by the manufacturing test tool set, without requiring the contents of that portion of the design to be implemented. The inputs and outputs of a portion of the design are examined for violations of the manufacturing test rules or guidelines. If there are no violations, the contents of this portion of the design are replaced with some basic contents which satisfy the manufacturing structure rules. The interconnections between logic blocks can then be tested using test generation tools to ensure the design does not violate manufacturing test rules or guidelines The compliance verification can thus be done much earlier in the design process than typically occurs.