Abstract: To increase the effective capacity of BIOS, an initial portion of the power on system reset (POST) code that is required to enable the system memory is stored in ROM in uncompressed form, and substantially the remaining portion of the BIOS code is stored in compressed form. Upon system initialization during a cold boot, the uncompressed portion of POST is executed from the ROM to enable the system memory, and then an image of the BIOS code is written to shadow memory. As BIOS code is needed during the remainder of the boot, the code is selectively decompressed from the shadow memory to another region of the system memory to which control is transferred. Variations based upon different boot scenarios are described.

Abstract: To increase the effective capacity of BIOS, an initial portion of the power on system reset (POST) code that is required to enable the system memory is stored in ROM in uncompressed form, and substantially the remaining portion of the BIOS code is stored in compressed form. Upon system initialization during a cold boot, the uncompressed portion of POST is executed from the ROM to enable the system memory, and then an image of the BIOS code is written to shadow memory. As BIOS code is needed during the remainder of the boot, the code is selectively decompressed from the shadow memory to another region of the system memory to which control is transferred. Variations based upon different boot scenarios are described.

Abstract: A system and method is provided for detecting and correcting a lost hardware interrupt generated by an input/output device in a multiple I/O port computer environment. The lost interrupt condition is caused by the simultaneous occurrence of (i) the reading and subsequent resetting of a interrupt request status bit in an I/O port by a device driver and (ii) the setting of the interrupt request status bit by an I/O device attached to the port. Because the interrupt request status bit is reset before it can be read, the device driver fails to see an acknowledgement of the previous data transmission to the I/O device, and the system encounters a deadlock condition. After a normal timeout timer expires the device driver terminates transmission of data and returns a "cancel or retry" message to the request originator. The present invention prevents a deadlock condition in this situation by providing a second timer in addition to and of significantly less duration than the normal timeout timer.

Abstract: A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and the volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor. The direct access storage device stores a second portion of operating system microcode which includes a plurality of modules.