Patents by Inventor Robert G Long
Robert G Long has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150048484Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.Type: ApplicationFiled: August 13, 2013Publication date: February 19, 2015Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Nathan Perkins, Jonathan Abrokwah, Ricky Snyder, Scott A. Rumery, Robert G. Long
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Patent number: 8941218Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.Type: GrantFiled: August 13, 2013Date of Patent: January 27, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Nathan Perkins, Jonathan Abrokwah, Ricky Snyder, Scott A. Rumery, Robert G. Long
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Patent number: 6903017Abstract: An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in the silicon layer of the IC. The titanium layer of the structure is at least partially alloyed with the aluminum layer, thereby restricting the ability of the titanium to getter the mobile impurities within the various layers of the IC. Despite the alloying of the titanium and aluminum, the metallization structure exhibits the superior contact resistance and electromigration properties associated with titanium.Type: GrantFiled: August 26, 2003Date of Patent: June 7, 2005Assignee: Agilent Technologies, Inc.Inventors: Ricky D. Snyder, Robert G Long, David W Hula, Mark D. Crook
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Publication number: 20040038453Abstract: An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in the silicon layer of the IC. The titanium layer of the structure is at least partially alloyed with the aluminum layer, thereby restricting the ability of the titanium to getter the mobile impurities within the various layers of the IC. Despite the alloying of the titanium and aluminum, the metallization structure exhibits the superior contact resistance and electromigration properties associated with titanium.Type: ApplicationFiled: August 26, 2003Publication date: February 26, 2004Inventors: Ricky D. Snyder, Robert G. Long, David W. Hula, Mark D. Crook
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Patent number: 6646346Abstract: An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in the silicon layer of the IC. The titanium layer of the structure is at least partially alloyed with the aluminum layer, thereby restricting the ability of the titanium to getter the mobile impurities within the various layers of the IC. Despite the alloying of the titanium and aluminum, the metallization structure exhibits the superior contact resistance and electromigration properties associated with titanium.Type: GrantFiled: October 27, 2000Date of Patent: November 11, 2003Assignee: Agilent Technologies, Inc.Inventors: Ricky D. Snyder, Robert G Long, David W Hula, Mark D. Crook
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Patent number: 6627866Abstract: An optical barrier made of tungsten (W) or titanium-tungsten (TiW). A layer of the optical barrier material is deposited over a transparent layer such as indium tin oxide (ITO). The optical barrier material is then patterned using photolithography processing steps and a dry etchant. The patterned optical barrier material acts as a light-shielding layer over a light-sensing device to form a dark reference device or dark pixel.Type: GrantFiled: October 5, 2001Date of Patent: September 30, 2003Assignee: Agilent Technologies, Inc.Inventors: David W. Hula, Robert G. Long
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Publication number: 20020092968Abstract: An optical barrier made of tungsten (W) or titanium-tungsten (TiW). A layer of the optical barrier material is deposited over a transparent layer such as indium tin oxide (ITO). The optical barrier material is then patterned using photolithography processing steps and a dry etchant. The patterned optical barrier material acts as a light-shielding layer over a light-sensing device to form a dark reference device or dark pixel.Type: ApplicationFiled: October 5, 2001Publication date: July 18, 2002Inventors: David W. Hula, Robert G. Long
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Patent number: 5539918Abstract: An adaptive data transfer channel providing means for a data management access method (AM) to define the channel subsystem data block transfer size and to transfer an extended data block (EDB) by a single channel transfer command to avoid repeated channel command word (CCW) command decode and status presentation operations. The adaptive scheme of this invention is transparent to the user and downwardly compatible with existing data record storage formats because it is independent of the user application program. The host software in the central processing complex (CPC) tests the peripheral data storage device (PDSD) to ensure compatibility with the EDB CCWs before selecting the channel program (CP) to be used for data block transfer in the subchannel. In the EDB format, the PDSD microcode permits the accumulation of logical data blocks (LDBs) from storage to form a single large EDB before transfer to the CPC responsive to a single transfer command.Type: GrantFiled: May 26, 1995Date of Patent: July 23, 1996Assignee: International Business Machines CorporationInventors: Vincent K. Allen, Scott M. Fry, Warren B. Harding, Robert G. Long, Jerry W. Pence, Wayne E. Rhoten, Richard A. Ripberger
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Patent number: 5517670Abstract: An adaptive data transfer channel providing means for a data management access method (AM) to define the channel subsystem data block transfer size and to transfer an extended data block (EDB) by a single channel transfer command to avoid repeated channel command word (CCW) command decode and status presentation operations. The adaptive scheme of this invention is transparent to the user and downwardly compatible with existing data record storage formats because it is independent of the user application program. The host software in the central processing complex (CPC) tests the peripheral data storage device (PDSD) to ensure compatibility with the EDB CCWs before selecting the channel program (CP) to be used for data block transfer in the subchannel. In the EDB format, the PDSD microcode permits the accumulation of logical data blocks (LDBs) from storage to form a single large EDB before transfer to the CPC responsive to a single transfer command.Type: GrantFiled: December 30, 1992Date of Patent: May 14, 1996Assignee: International Business Machines CorporationInventors: Vincent K. Allen, Scott M. Fry, Warren B. Harding, Robert G. Long, Jerry W. Pence, Wayne E. Rhoten, Richard A. Ripberger
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Patent number: 4053714Abstract: This invention relates to data transmission system of the type where a plurality of transmitters are located at a location remote from a receiver and are adapted to transmit information from their location in turn to the receiver. The transmitters in the case of this invention are each self-powered and have their own transmitter timer associated with them. They are all set to operate from time zero by a master timer and their individual power sources are recharged for the power dissipated in each of their transmissions by a charging pulse that is received over the transmission line. The resetting of the transmitter timers to cause them to transmit in sequence is done during the recharging period which follows the transmissions of the series of transmitters.Type: GrantFiled: April 6, 1976Date of Patent: October 11, 1977Assignee: Canadian PGL Electronics Inc.Inventor: Robert G. Long