Abstract: Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents.

Abstract: Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents.

Abstract: One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.

Abstract: One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.

Abstract: A method, apparatus, and system are provided for early data return indication mechanism. According to one embodiment, data cache is accessed for data in response to a request for the data, the request received from an instruction source, and the request waits for the data to be retrieved from memory if the data is not located in the data cache, and an early data ready indication is received at a resource scheduler, the early data ready indication being received prior to receiving a data ready indication referring to the data being ready to be retrieved from the memory.