Abstract: The invention provides an oscillator apparatus having a plurality of stages, with each stage of the plurality of stages having an output node, and with a plurality of input transistors within each stage. The various output nodes are coupled to the transistor inputs of the various stages, such that for the nth stage of the plurality of stages, the input to jth transistor, of the plurality of input transistors, is coupled to the (n?j)th output node, and wherein (n?j) is determined modulo N, where “N” is a total number of the plurality of stages and “j” is a transistor number of the plurality of input transistors within each stage. The various embodiments of the oscillator include oscillators with 6 or more stages and with 3 or more inputs per stage, plus any load input transistor, including 8 and 16 stage oscillators to produce a multiplicity of phases for any selected use.

Abstract: The invention provides a method, program and system for designing an oscillator apparatus having a plurality of stages, with each stage of the plurality of stages having an output node, and with a plurality of input transistors within each stage. The various output nodes are coupled to the transistor inputs of the various stages, such that for the nth stage of the plurality of stages, the input to a jth input transistor, of the plurality of input transistors, is coupled to the (n−j)th output node, and wherein (n−j) is determined modulo N, where “N” is a total number of the plurality of stages and “j” is a transistor number of the plurality of input transistors within each stage. The methodology determines relative sizes of each input transistor within a stage for a given number of stages, a total transconductance of the input transistors per stage, and a minimum relative attenuation of undesired modes.

Abstract: The invention provides a method, program and system for designing an oscillator apparatus having a plurality of stages, with each stage of the plurality of stages having an output node, and with a plurality of input transistors within each stage. The various output nodes are coupled to the transistor inputs of the various stages, such that for the nth stage of the plurality of stages, the input to a jth input transistor, of the plurality of input transistors, is coupled to the (n−j)th output node, and wherein (n−j) is determined modulo N, where “N” is a total number of the plurality of stages and “j” is a transistor number of the plurality of input transistors within each stage. The methodology determines relative sizes of each input transistor within a stage for a given number of stages, a total transconductance of the input transistors per stage, and a minimum relative attenuation of undesired modes.