Patents by Inventor Robert G. Sheldon

Robert G. Sheldon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817456
    Abstract: An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 27, 2020
    Assignee: Oracle International Corporation
    Inventors: John R. Feehrer, Matthew Cohen, Rahoul Puri, Tayfun Kocaoglu, John Johnson, David Kahn, Alan Adamson, Sriram Jayakumar, Julia Harper, Robert G. Sheldon, Mark Kanda, Aruna Jayakumar
  • Publication number: 20170286354
    Abstract: An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: John R. Feehrer, Matthew Cohen, Rahoul Puri, Tayfun Kocaoglu, John Johnson, David Kahn, Alan Adamson, Sriram Jayakumar, Julia Harper, Robert G. Sheldon, Mark Kanda
  • Patent number: 5976340
    Abstract: A method is disclosed for fabricating a low cost, elevated-temperature resistant part with a serrated surface and elevated-temperature structural properties similar to (within fifty percent (50%)) a superalloy material comprising the steps of: forming a master tool having the desired serrated surface; electro-forming the elevated-temperature resistant part by depositing three alloying elements comprising nickel, cobalt and manganese onto the master tool in the amounts of about 60%-70% nickel, 40%-30% cobalt and 0.05%-0.10% manganese; and separating the elevated-temperature resistant part from master tool.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: November 2, 1999
    Assignee: Lockheed Martin Corporation
    Inventors: Robert G. Sheldon, Eric G. Smith
  • Patent number: 5230259
    Abstract: A method of making a structure having a plurality of serrations on a surface is provided wherein each serration is positioned at a specific location along the surface, has first and second sides with specific lengths, and has effectively zero radius internal and external corners. In detail, the method comprising the steps of: providing a plurality of sheets of material having opposed principal surfaces, each said sheet having a thickness equal to the specific thickness of one of the first sides of the serrations; stacking said plurality of sheets of material in a staggered relationship such that said thicknesses of said sheets of material are in an order corresponding to the order of the first sides of the serrations and the distance between the ends of the adjacent ends of said sheets of material are in an order corresponding to the second sides of the serrations; and joining said stacked plurality of sheets of material together forming a joined stack with at least one end having a serrated surface thereon.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: July 27, 1993
    Assignee: Lockheed Corporation
    Inventor: Robert G. Sheldon
  • Patent number: 5146460
    Abstract: Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing.
    Type: Grant
    Filed: February 16, 1990
    Date of Patent: September 8, 1992
    Assignee: International Business Machines
    Inventors: Dennis F. Ackerman, David R. Bender, Salina S. Chu, George R. Deibert, Gary G. Hallock, David E. Lackey, Robert G. Sheldon, Thomas A. Stranko