Patents by Inventor Robert G. Southworth
Robert G. Southworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11671194Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.Type: GrantFiled: November 16, 2021Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Mark A. Bordogna, Janardhan H. Satyanarayana, Larry N. Wakeman, Robert G. Southworth, Mika Nystroem
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Publication number: 20220077946Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.Type: ApplicationFiled: November 16, 2021Publication date: March 10, 2022Applicant: Intel CorporationInventors: Mark A. Bordogna, Janardhan H. Satyanarayana, Larry N. Wakeman, Robert G. Southworth, Mika Nystroem
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Patent number: 11212024Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.Type: GrantFiled: April 7, 2017Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: Mark A. Bordogna, Janardhan H. Satyanarayana, Larry N. Wakeman, Robert G. Southworth, Mika Nystroem
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Publication number: 20210320875Abstract: A network switch includes a memory device to store a stream information of a plurality of data streams being handled by the network switch, the stream information including a stream identifier, a stream service level agreement (SLA), and a stream traffic type; accelerator circuitry to apply stream transformation functions to data streams; telemetry circuitry to monitor egress ports of the network switch; and scheduler circuitry to: receive telemetry data from the telemetry circuitry to determine that a utilization of egress ports of the network switch is over a threshold utilization; determine a selected data stream of the plurality of data streams to transform; use the accelerator circuitry to transform the selected data stream to produce a transformed data stream, wherein the transformed data stream complies with a corresponding stream SLA; and transmit the transformed data stream on an egress port.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas E. Willis, Timothy Verrall, Robert G. Southworth
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Publication number: 20210203428Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.Type: ApplicationFiled: April 7, 2017Publication date: July 1, 2021Inventors: Mark A. BORDOGNA, Janardhan H. SATYANARAYANA, Larry N. WAKEMAN, Robert G. SOUTHWORTH, Mika NYSTROEM
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Publication number: 20200412649Abstract: A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Patent number: 10785150Abstract: A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.Type: GrantFiled: September 25, 2015Date of Patent: September 22, 2020Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20200159654Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Inventors: Sanjeev Jain, Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Patent number: 10621080Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.Type: GrantFiled: April 1, 2016Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Sanjeev Jain, Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Patent number: 9992125Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: GrantFiled: August 16, 2016Date of Patent: June 5, 2018Assignee: Intel CorporationInventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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Publication number: 20170286006Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Sanjeev Jain, Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20170093708Abstract: A communication packet processing device may include a control stage coupled to receive multiple headers of a packet comprised of multiple words, and to determine a destination lane for each word of the multiple headers by counting previous words of the headers. The device may also include a level 1 permutation circuit coupled to the control stage to place each word into a correct lane responsive to the determined destination lane, and a level 2 permutation circuit coupled to the level 1 permutation t circuit o place each word into a correct designation lane responsive to the determined destination lane. Additional embodiments are also described.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20170093709Abstract: A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20160359754Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: ApplicationFiled: August 16, 2016Publication date: December 8, 2016Inventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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Patent number: 9426096Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: GrantFiled: May 21, 2014Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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Publication number: 20150341277Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Inventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb