Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: Structures for laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices, as well as methods of forming laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices. A gate electrode is arranged to extend about a semiconductor fin projecting from a substrate. A drain region is arranged in the substrate, and a source region is coupled with the semiconductor fin. The source region is arranged over the semiconductor fin. A drift region is arranged in the substrate between the drain region and the semiconductor fin. The drain region, source region, and drift region have a given conductivity type. The drift region has a lower electrical conductivity than the drain region.

Abstract: Structures for laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices, as well as methods of forming laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices. A gate electrode is arranged to extend about a semiconductor fin projecting from a substrate. A drain region is arranged in the substrate, and a source region is coupled with the semiconductor fin. The source region is arranged over the semiconductor fin. A drift region is arranged in the substrate between the drain region and the semiconductor fin. The drain region, source region, and drift region have a given conductivity type. The drift region has a lower electrical conductivity than the drain region.

Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.

Abstract: An external current injection source is provided to individual fingers of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.

Abstract: Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.

Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.