Patents by Inventor Robert Gibbins
Robert Gibbins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11538511Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.Type: GrantFiled: February 11, 2021Date of Patent: December 27, 2022Assignee: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski
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Patent number: 11483007Abstract: Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.Type: GrantFiled: June 23, 2021Date of Patent: October 25, 2022Assignee: Ciena CorporationInventors: Jerry Yee-Tung Lam, Douglas Stuart McPherson, Robert Gibbins, Naim Ben-Hamida
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Publication number: 20220254394Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Applicant: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski
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Patent number: 11245401Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.Type: GrantFiled: December 16, 2020Date of Patent: February 8, 2022Assignee: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson, Robert Gibbins, Anna Sakharova
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Publication number: 20210313992Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.Type: ApplicationFiled: December 16, 2020Publication date: October 7, 2021Applicant: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson, Robert Gibbins, Anna Sakharova
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Patent number: 10903841Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.Type: GrantFiled: April 3, 2020Date of Patent: January 26, 2021Assignee: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson, Robert Gibbins, Anna Sakharova
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Patent number: 7042913Abstract: A technique for provisioning cross-connects in network switching environment includes writing a first set of data into a first memory element during a first time interval and writing a second set of data into a second memory element during a second time interval. The technique reads a portion of the first set of data from the first memory element during the second time interval and reads a portion of the second set of data from the second memory element during a third time interval, and determines the first, second, and third time intervals based on a format of the sets of data, with the first time interval ending before the second time interval begins, and the second time interval ending before the third time interval begins.Type: GrantFiled: September 30, 2003Date of Patent: May 9, 2006Assignee: Nortel Networks LimitedInventors: Andrew Jarabek, Aris Tombul, Robert Gibbins
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Publication number: 20050071594Abstract: A technique for provisioning cross-connects in network switching environment includes writing a first set of data into a first memory element during a first time interval and writing a second set of data into a second memory element during a second time interval. The technique reads a portion of the first set of data from the first memory element during the second time interval and reads a portion of the second set of data from the second memory element during a third time interval, and determines the first, second, and third time intervals based on a format of the sets of data, with the first time interval ending before the second time interval begins, and the second time interval ending before the third time interval begins.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Inventors: Andrew Jarabek, Aris Tombul, Robert Gibbins
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Publication number: 20030014610Abstract: A system for facilitating sharing of experience comprises a database (52) storing people identifiers and features of their experience. A user can query the database (52) from a client machine (1, 2) using details of a task that they are undertaking to obtained a ranked list of people with relevant experience.Type: ApplicationFiled: August 30, 2002Publication date: January 16, 2003Inventors: Simon Mills, Robert Gibbins