Abstract: An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14, 16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-or gate (52), and at least one delay line (58A or 58B) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel.

Abstract: A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access back-up unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. If the data is not available in the associative memory unit during a reading operation, or if the central processor is transferring data to the address location during a writing operation, the associative memory unit causes the back-up unit to perform a corresponding memory cycle.