Abstract: Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.

Abstract: The invention is directed to validating a specified manufacturing test rule, which pertains to an electronic component. The method includes generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected. The method further comprises constructing a testbench to prepare testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase.

Abstract: A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.

Abstract: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.

Abstract: Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.

Abstract: A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.

Abstract: The invention is generally directed to a method and apparatus for validating a specified manufacturing test rule, which pertains to an electronic component. One embodiment comprising a method includes the step of generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected, when the stimulus is applied to the electronic component. The method further comprises constructing a testbench to prepare each of a plurality of testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase.

Abstract: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.

Abstract: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.

Abstract: Scan chains are designed for an IC based on test coverage for functional logic units, Before physical placement the scan circuit elements are assigned scan attributes which define which scan circuit elements must remain coupled and also defines which groups of scan circuit elements must remain in selected groups. The scan chains and the logic are physically placed and location data on the scan circuit elements are determined from the placement data. Using the scan attributes, single scan circuit elements and scan circuit elements that must remain connected (sub-scan chains) are re-allocated across a same number of new scan chains. These scan circuit elements are rewired using an algorithm that minimizes scan path lengths within the new scan chains.

Abstract: Descriptive statements representative of a communication level coupling the functional logic of an integrated circuit to the external environment is translated into complex functional specification language for input to hardware design programs. Plain language within the functional specifications is converted to proper design language to implement hardware described by the functional specification.

Abstract: Stuck-at fault, shorted and open circuit conditions occurring in the differential inputs to Differential Receivers on a Large Scale Integrated (LSI) chip are detected by a test circuit arrangement fabricated on the chip. The test circuit arrangement includes Pass Gate devices operatively coupled to the differential inputs and an Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull devices are coupled to the Pass Gate devices and the differential inputs. By activating the Pass Gate devices and applying a test sequence to the differential inputs, the state of the output of the XNOR circuit indicates if an open circuit, stuck-at or short exists in the inputs to the Differential Receiver.

Abstract: Stuck-at fault, shorted and open circuit conditions occurring in the differential inputs to Differential Receivers on a Large Scale Integrated (LSI) chip are detected by a test circuit arrangement fabricated on the chip. The test circuit arrangement includes Pass Gate devices operatively coupled to the differential inputs and an Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull devices are coupled to the Pass Gate devices and the differential inputs. By activating the Pass Gate devices and applying a test sequence to the differential inputs, the state of the output of the XNOR circuit indicates if an open circuit, stuck-at or short exists in the inputs to the Differential Receiver.

Abstract: An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.