Abstract: Embodiments of the present invention comprises a system, method, and apparatus that provides for the utilization of a relatively real-time or near real-time interpretation or translation that may be utilized preferably for a relatively short duration of time on a network. A preferred embodiment of the present invention provides online, real-time, short-duration interpreting services in a network-based format. In preferred embodiments, the interpreting system comprises at least one provider computer, such as a server, wherein the provider computer is capable of communicating with user computers via a network. In one preferred embodiment, the provider computer provides a series of web pages that allow access to the interpreting system, including, but not limited to, a request for service page, wherein a user can access the system and input a request for interpreting services. Interpreting services are then provided to a user and a third party desiring to communicate with the user via the network.

Abstract: The present invention is directed to a process for coating a substrate in a rotating drum, wherein a pocket is created in a substrate bed into which pocket coating materials are delivered. Also provided is a controlled release product produced according to this process, and an apparatus for carrying out the process.

Abstract: According to one embodiment of the present invention, a method for protecting content in a broadcast-encryption-based system, where the devices in the system receive a recording key table. Each device generates a set of recording keys from the recording key table using a media key variant calculated from the broadcast encryption system's media key block. The digital content is encrypted in a title key picked by the recorder. The selected title key is also encrypted in each one of the recorder's generated recording keys. To play back the content, a player uses one of its generated recording keys to decrypt the title key and the decrypt the content. The recording key table is designed so that any two devices are guaranteed to have at least one key in common during normal operation, although during a forensic situation, this rule can be abandoned.

Abstract: Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.

Abstract: A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.

Abstract: The invention is generally directed to a method and apparatus for validating a specified manufacturing test rule, which pertains to an electronic component. One embodiment comprising a method includes the step of generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected, when the stimulus is applied to the electronic component. The method further comprises constructing a testbench to prepare each of a plurality of testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase.

Abstract: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.

Abstract: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.

Abstract: A U-head plate is provided having a channel for capturing a base plate of a shoring apparatus. A pair of inwardly opposing L-shaped extensions extending downwardly from the U-head plate forms the channel. A latch attached to the U-head plate has a tongue for engaging a notch in the base plate of the shoring apparatus upon capture of the base plate of the shoring apparatus within the channel. The tongue is biased toward the notch by a spring.

Abstract: A purified preparation of a peptide consisting essentially of an amino acid sequence identical to that of a segment of a naturally-occurring human protein, said segment being of 10 to 30 residues in length, inclusive, wherein said peptide binds to a human major histocompatibility complex (MHC) class II allotype.

Abstract: Scan chains are designed for an IC based on test coverage for functional logic units, Before physical placement the scan circuit elements are assigned scan attributes which define which scan circuit elements must remain coupled and also defines which groups of scan circuit elements must remain in selected groups. The scan chains and the logic are physically placed and location data on the scan circuit elements are determined from the placement data. Using the scan attributes, single scan circuit elements and scan circuit elements that must remain connected (sub-scan chains) are re-allocated across a same number of new scan chains. These scan circuit elements are rewired using an algorithm that minimizes scan path lengths within the new scan chains.

Abstract: A U-head plate is provided having a channel for capturing a base plate of a shoring apparatus. A pair of inwardly opposing L-shaped extensions extending downwardly from the U-head plate forms the channel. A latch attached to the U-head plate has a tongue for engaging a notch in the base plate of the shoring apparatus upon capture of the base plate of the shoring apparatus within the channel. The tongue is biased toward the notch by a spring.

Abstract: Descriptive statements representative of a communication level coupling the functional logic of an integrated circuit to the external environment is translated into complex functional specification language for input to hardware design programs. Plain language within the functional specifications is converted to proper design language to implement hardware described by the functional specification.

Abstract: A purified preparation of a peptide consisting essentially of an amino acid sequence identical to that of a segment of a naturally-occurring human protein, said segment being of 10 to 30 residues in length, inclusive, wherein said peptide binds to a human major histocompatibility complex (MHC) class II allotype.

Abstract: Stuck-at fault, shorted and open circuit conditions occurring in the differential inputs to Differential Receivers on a Large Scale Integrated (LSI) chip are detected by a test circuit arrangement fabricated on the chip. The test circuit arrangement includes Pass Gate devices operatively coupled to the differential inputs and an Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull devices are coupled to the Pass Gate devices and the differential inputs. By activating the Pass Gate devices and applying a test sequence to the differential inputs, the state of the output of the XNOR circuit indicates if an open circuit, stuck-at or short exists in the inputs to the Differential Receiver.

Abstract: Stuck-at fault, shorted and open circuit conditions occurring in the differential inputs to Differential Receivers on a Large Scale Integrated (LSI) chip are detected by a test circuit arrangement fabricated on the chip. The test circuit arrangement includes Pass Gate devices operatively coupled to the differential inputs and an Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull devices are coupled to the Pass Gate devices and the differential inputs. By activating the Pass Gate devices and applying a test sequence to the differential inputs, the state of the output of the XNOR circuit indicates if an open circuit, stuck-at or short exists in the inputs to the Differential Receiver.

Abstract: An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.

Abstract: A purified preparation of a peptide consisting essentially of an amino acid sequence identical to that of a segment of a naturally-occurring human protein, said segment being of 10 to 30 residues in length, inclusive, wherein said peptide binds to a human major histocompatibility complex (MHC) class II allotype.

Abstract: A new variety of orchid plant of the Oncidiinae Intergeneric group, Brassidium, named EXOTIC ORCHID ‘White Knight’, distinguished in part by a compact size, highly contrasted flower, and growing quickly from in-vitro culture to flowering.

Abstract: A new variety of orchid plant of the Oncidiinae Intergeneric group, of the Maclellanara nothogenera, named EXOTIC ORCHID ‘Golden Gambol’, distinguished in part by a rich butter yellow background, highly contrasted with chocolate blotching, and growing without cultural issues from in-vitro culture to in-vivo flowering. EXOTIC ORCHID ‘Golden Gambol’ grows very fast to sexual maturity and flowers freely.