Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

Abstract: Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

Abstract: A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.

Abstract: A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

Abstract: Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.

Abstract: A horse stirrup which also functions as a mounting aid by providing, in the same assembly, a foot supporting platform for riding, as well as a convenient, lower level platform for mounting. The mounting platform, and related structure, also function, in cooperation with the riding platform, to reduce the exposure of the rider to stirrup foot lock in case of a fall.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving subsets of instructions corresponding to different portions of a program, each subset assigned to one of the computation units; scheduling instructions in a given subset for execution on the assigned computation unit, including scheduling communication instructions that send to or receive from a different computation unit over the interconnection network; allocating registers in a given computation unit for storing values accessed by instructions in a subset assigned to the given computation unit; and scheduling instructions after allocating registers to account for spills of values stored in allocated register to memory, preserving the order of communication instructions scheduled before allocating registers.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving an initial partitioning of instructions into initial subsets corresponding to different portions of a program; forming a refined partitioning of the instructions into refined subsets each including one or more of the initial subsets, including determining whether to combine a first subset and a second subset to form a third subset according to a comparison of a communication cost between the first subset and second subset and a load cost of the third subset that is based at least in part on a number of instructions issued per cycle by a computation unit; and assigning each refined subset of instructions to one of the computation units for execution on the assigned computation unit.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.

Abstract: A method and system of detecting vulnerabilities in source code. Source code is parsed into an intermediate representation. Models (e.g., in the form of lattices) are derived for the variables in the code and for the variables and/or expressions used in conjunction with routine calls. The models are then analyzed in conjunction with pre-specified rules about the routines to determine if the routine call posses one or more of pre-selected vulnerabilities.

Abstract: Methods and systems of detecting vulnerabilities in source code using inter-procedural analysis of source code. Vulnerabilities in a pre-existing source code listing are detected. The variables in the source code listing are modeled in the context of at least one of the inherent control flow and inherent data flow. The variable models are used to create models of arguments to routine calls in the source code listing. The source code listing is modeled with a call graph to represent routine call interactions expressed in the source code listing. The arguments to routine calls are modeled to account for inter-procedural effects and dependencies on the arguments as expressed in the source code listing.

Abstract: A horse stirrup which also functions as a mounting aid by providing, in the same assembly, a foot supporting platform for riding, as well as a convenient, lower level platform for mounting. The mounting platform, and related structure, also function, in cooperation with the riding platform, to reduce the exposure of the rider to stirrup foot lock in case of a fall.

Abstract: A stirrup assembly for aiding a rider when mounting a horse provides a stirrup assembly wherein part or all of the side of a stirrup can be rotated down into a locked horizontal position to become a step. The act of pulling down the movable side part compresses a strong return spring. When the movable side part is fully down, a latch is set which keeps it from returning. What was part of the stirrup side can now be used as a step for mounting and is quickly returned to its original upright position by the return spring when the rider steps on the latch release.