Abstract: Particular embodiments described herein can offer a method that includes determining that a first reported latency tolerance associated with at least one first device has not been received, and causing determination of a platform latency tolerance based, at least in part, on a first predefined latency tolerance, which is to serve as a substitute for the first reported latency tolerance.

Abstract: Particular embodiments described herein provide for an apparatus that includes a means for determining a power state for a device connected to a system, a means for determining that the device should change power states, and means for sending a signal to the device to put the device in a D3-cold state while the system is a GO/SO state. In an embodiment, the device is a peripheral component interconnect (PCI) device. Also, the particular example implementation can include means for sending a WAKE# signal from a controller to the device to cause the device to exit the D3-cold state, wherein the WAKE# signal was sent from a designated WAKE# signal pin on the controller. In some embodiments, the WAKE# signal is not sent to other devices in the system.

Abstract: In some embodiments, a PPM interface for a computing platform may he provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: A dynamic shower system comprises a user actuator indicating said user's desire to use recycled water during the shower, a shower head, a drain, a first valve capable of selecting water to be emitted from said shower head from a potable water source or water from a mixture of potable water and recycled water from said drain, and a processor, said processor in communication with said user actuator and said first valve wherein said first valve is capable of being controlled by said processor. The shower system may be capable of dynamically switching between said potable water only and said mixture of potable and recycled water depending upon the certain conditions being detected by said processor.

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.

Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.

Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.

Abstract: In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described.

Abstract: A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals.

Abstract: In some embodiments, a system comprises a host system comprising an industry standard interface, a peripheral device coupled to the host device via the industry standard interface, and logic in the host system to confirm that the host device supports an enhanced feature, identify at least one pin on the industry standard interface on which the enhanced feature may be implemented, enable support for the enhanced feature on the at least one pin, and route communication traffic associated with the enhanced feature to the at least one pin. Other embodiments may be described.

Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.

Abstract: In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface, wherein the USB device cooperate to defer one or more data traffic exchanges by passing control messages via a sideband communication link. Other embodiments may be described.

Abstract: In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface, wherein the USB device cooperate to defer one or more data traffic exchanges by passing control messages via a sideband communication link. Other embodiments may be described.

Abstract: In some embodiments, a system comprises a host system comprising an industry standard interface, a peripheral device coupled to the host device via the industry standard interface, and logic in the host system to confirm that the host device supports an enhanced feature, identify at least one pin on the industry standard interface on which the enhanced feature may be implemented, enable support for the enhanced feature on the at least one pin, and route communication traffic associated with the enhanced feature to the at least one pin. Other embodiments may be described.

Abstract: In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described.

Abstract: A method and apparatus is described herein for dynamically allocating resources to root ports. Upon initialization of a system, resources, such as memory space, I/O space, and/or bus numbers are allocated to devices and corresponding windows are assigned to root ports present upstream from those devices. A remaining amount of resources are reserved into a resource pool. When a new device is inserted at runtime, a handler services the insertion notification by assigning an appropriate resource window from the resource pool to the root port upstream from the newly added device. In contrast, upon removal the window of resources are re-assigned back to the resource pool.

Abstract: A method and apparatus is described herein are for managing interconnect controllers. When a downstream device is removed from a system, the controller coupled to the devce is placed in a low-power state to save power and ejected from an operating system. Detection circuitry in the controller is also disabled. However, periodically the circuitry is re-enabled to determine if a downstream device has been connected. Upon insertion, the controller is powered on and enabled in the operating system.

Abstract: A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals.