Patents by Inventor Robert Gravelle

Robert Gravelle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060064268
    Abstract: Methods, systems, and apparatuses provide dynamic creation and modification of wafer test maps. Test plans are defined for a testing session of a wafer lot. The test plan is associated with a number of seed map patterns. During a wafer lot testing session, test results are dynamically obtained and examined at run-time of a test. Moreover, the seed map patterns are overlaid on the test sites defined in the test plan. If the test result statistics are outside of defined threshold tolerance levels, then a new wafer test map is created or modified at run-time, according to corresponding seed map patterns. If seed map patterns are within the intersection of valid test sites, then seed map patterns are created at run-time.
    Type: Application
    Filed: November 3, 2005
    Publication date: March 23, 2006
    Inventors: Michael Dorough, Robert Gravelle, Sergey Velichko