Patents by Inventor Robert Gries

Robert Gries has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8219880
    Abstract: In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 10, 2012
    Assignee: Apple Inc.
    Inventors: Brian P. Lilly, Robert Gries, Sridhar P. Subramanian, Sukalpa Biswas, Hao Chen
  • Publication number: 20120017135
    Abstract: In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
    Type: Application
    Filed: September 27, 2011
    Publication date: January 19, 2012
    Inventors: Brian P. Lilly, Robert Gries, Sridhar P. Subramanian, Sukalpa Biswas, Hao Chen
  • Patent number: 8055975
    Abstract: In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 8, 2011
    Assignee: Apple Inc.
    Inventors: Brian P. Lilly, Robert Gries, Sridhar P. Subramanian, Sukalpa Biswas, Hao Chen
  • Publication number: 20080307286
    Abstract: In one embodiment, an apparatus comprises a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission comprising M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
    Type: Application
    Filed: June 5, 2007
    Publication date: December 11, 2008
    Inventors: Brian P. Lilly, Robert Gries, Sridhar P. Subramanian, Sukalpa Biswas, Hao Chen
  • Publication number: 20050212976
    Abstract: A video display includes a scanner operable at a first frequency and a higher second frequency. A switch mode power supply drives a transformer with three secondaries. First and second rectifiers & filters are associated with the first and second secondaries. A rectifier is coupled to the third secondary and by way of a switch to the first filter. Feedback from the first filter controls the SMPS. In a first operating mode, the scanner is operated at the first frequency, the switch is open, the scanner supply is a first voltage from the first filter, and ancillary equipment is supplied with a third voltage by the second filter. In a second operating mode, the scanner is operated at the second frequency, the switch is closed, the scanner supply is a second voltage, higher than the first, from the first filter, and ancillary equipment is supplied with the same third voltage.
    Type: Application
    Filed: April 16, 2003
    Publication date: September 29, 2005
    Inventors: Snehali Choksi, Robert Gries, Kevin Williams, David Jackson, Robert Watson III