Abstract: A computer system which is reconfigurable to provide separate ergonomically advantageous positions for keyboard input and for stylus input. A primary system chassis contains a bay in its underside where a detachable keyboard can be stored. For one-hand stylus input, the keyboard is left in its bay while the display is mounted flat on top of the system chassis. For keyboard input, the keyboard is mounted on the system chassis, and the display is supported at an angle which makes it easily visible to a user typing on the keyboard.

Abstract: A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of the first channel layer and an insulating layer is formed on the surface of the first source/drain layer. A second source/drain layer of the second conductivity type is formed on the surface of the insulating layer and a second channel layer of said first conductivity is formed on the surface of the second source/drain layer. A third source/drain layer of the second conductivity type is formed on the surface of the second channel layer. Gate circuitry is vertically disposed on an edge perpendicular to the plane and adjacent to the first and second channel layers and insulated therefrom.

Abstract: Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices. The TiN gates in the second set of transistors and the TiN interconnect are formed by providing a thin film insulator pattern, depositing a titanium layer overall, heating the titanium in a nitrogen bearing atmosphere, and subsequently etching the titanium nitride obtained.

Abstract: Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

Abstract: Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

Abstract: A new integrated circuit structure which includes two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices.

Abstract: Disclosed is a process for making VLSI integrated circuits and a local interconnect system, wherein first poly, second poly and moat are all interconnected in any desired pattern by a TiN local interconnect. No masks are required beyond those which would be required for the two poly levels and local interconnect capability anyway.