Abstract: A transmission system includes a transmission path from a transmitting station to a receiving station for both voice telephone service occupying the frequency spectrum below a predetermined frequency f.sub.1 and for data service occupying the frequency spectrum above another predetermined frequency f.sub.3, where f.sub.3 is substantially higher than f.sub.1, a plurality of telephone sets at said receiving station connected in parallel with one another to the transmission path, and where each of the telephone sets has an on-hook state which presents a substantially infinite resistance to the transmission path and an off-hook state which presents a predetermined resistance R to the transmission path. A plurality of separate and substantially identical multi-pole low-pass filters are provided for connection between the transmission path and respective ones of the telephone sets, where each of the low-pass filters has a -3 dB frequency f.sub.2 which lies between f.sub.1 and f.sub.

Abstract: The present invention describes a circuit which allows a data stream to be scrambled by continuously running uninterrupted Pseudo Random sequence without multiplying errors. This is accomplished by allowing a register in the Pseudo Random scrambling receiver to acquire synchronization with a register in the Pseudo Random scrambling transmitter such that the two registers run independently through the same maximal length Pseudo Random sequence without further need for communication with each other. Bit errors occurring between the transmitter and receiver do not cause the scrambling registers at the two ends to become out of synchronization and they remain in synchronism unless a timing slip occurs to cause the transmitter and receiver to lose synchronization.

Abstract: This invention is a circuit for generating a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position.

Abstract: A level comparator is used to check the incoming message header pulse amplitude and if it is of a level higher than an established level a signal is transmitted to update a digital counter whose digital output is converted by a digital to analog converter to establish an increased analog reference level. If the incoming message header is lower the counter is decremented to establish a lower reference level. Then the levels of any signals present at fixed intervals after the header or sync pulse are measured and recorded. These measured levels constitute the value of correction required for subsequent pulses and are added to or subtracted from following data pulses as required.

Abstract: This invention is a circuit for detecting a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position. In addition, the incoming data stream may be connected directly to the shift register mechanism.

Abstract: A circuit arranged to measure and correct for transmission line induced disturbances at discrete intervals after receipt of a header pulse by recording the presence of any voltage deviating from a set level. These levels are registered and during receipt of the data pulses are utilized at times corresponding to the relative position of the preceding data pulses to modify subsequent data bits.

Abstract: An arrangement for monitoring the admittance of a line during a frequency sweep is disclosed which upon detection of the characteristic admittance level determines the loaded or unloaded status of a transmission line. Output logic associated with detection circuits provides a digital indication of the status detected.

Abstract: A circuit for monitoring the alignment of analog-to-digital converters. The digital output signal from a converter under test is separated into positive and negative component signals which are compared by a subtraction circuit. A difference signal is then generated by the subtraction circuit to represent the required converter adjustment. Also included are adder circuitry for a sum output and provisions for analog display.

Abstract: A parity checking circuit for use in multifrequency tone receivers is disclosed wherein associated receivers are made less susceptible to digit simulation when talking is present, by verifying that the same two tones are present for the entire parity timing period.

Abstract: A circuit for generating precise tone signals for use in telecommunications systems, such as dial tone, busy tone, ringback tone, etc. the circuit provides tone signals at a level suitable for application for distribution throughout a telephone central office. A facility for providing interrupt of the signals at either a 60 or 120 IPM rate is included.